Semiconductor integrated circuit device with reduced leakage current
View Patent ↗The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
1. A semiconductor integrated circuit device comprising:
a logic circuit including an N channel type MOS transistor and P channel type MOS transistor, drains of said N channel type and P channel type MOS transistors being coupled to each other; and
a switch circuit for keeping a source line at a first potential in a first condition, and keeping said source line at a second potential in a second condition,
wherein a source electrode of said N channel type MOS transistor is coupled to said source line,
wherein said source line is coupled to said switch circuit; and
wherein an insulating layer for use in a gate of either of said N channel type MOS transistor or said P channel type MOS transistor has a thickness of 4 nm or less.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein a substrate electrode of said N channel type MOS transistor is set to said first potential.
3. The semiconductor integrated circuit device according to claim 1 ,
wherein a substrate electrode of said N channel type MOS transistor is coupled to said source line.
4. The semiconductor integrated circuit device according to claim 3 ,
wherein a substrate electrode of said N channel type MOS transistor is set to said first potential.
5. The semiconductor integrated circuit device according to claim 1 ,
wherein a gate tunnel leakage current of either of said N channel type MOS transistor or P channel type MOS transistor in an active mode is at least 10 −12 A/μm 2 .
6. The semiconductor integrated circuit device according to claim 5 ,
wherein a substrate electrode of said N channel type MOS transistor is set to said first potential.
7. The semiconductor integrated circuit device according to claim 5 ,
wherein a substrate electrode of said N channel type MOS transistor is coupled to said source line.
8. The semiconductor integrated circuit device according to claim 7 ,
wherein a substrate electrode of said N channel type MOS transistor is set to said first potential.
9. A semiconductor integrated circuit device comprising:
a logic circuit including an N channel type MOS transistor and P channel type MOS transistor, drains of said N channel type and P channel type MOS transistors being coupled to each other; and
a switch circuit for keeping a source line at a first potential in a first condition, and keeping said source line at a second potential in a second condition,
wherein a source electrode of said N channel type MOS transistor is coupled to said source line,
wherein said source line is coupled to said switch circuit; and
wherein a gate tunnel leakage current of either of said N channel type MOS transistor or P channel type MOS transistor in an active mode is at least 10 −12 A/μm 2 .
10. The semiconductor integrated circuit device according to claim 9 ,
wherein a substrate electrode of said N channel type MOS transistor is set to said first potential.
11. The semiconductor integrated circuit device according to claim 9 ,
wherein a substrate electrode of said N channel type MOS transistor is coupled to said source line.
12. The semiconductor integrated circuit device according to claim 11 ,
wherein a substrate electrode of said N channel type MOS transistor is set to said first potential.