Semiconductor devices and methods of forming interconnection lines therein

1. A method of forming an interconnection line of a semiconductor device, comprising:

sequentially forming a metal layer and a conductive layer on the metal layer over a semiconductor substrate including a lower interlayer insulating layer,

forming a first conductive layer pattern including a hole to partially expose the metal layer by patterning the conductive layer;

forming a mask pattern which fills the hole of the first conductive layer pattern and masks the first conductive layer pattern around the hole;

dividedly forming a second conductive layer pattern by etching the first conductive layer pattern using the mask pattern;

forming a first metal layer pattern including a protruding portion by partially etching the metal layer up to a predetermined thickness with the use of both the mask pattern and the second conductive layer pattern;

removing the mask pattern;

forming a spacer on a sidewall of each of the second conductive layer pattern and the protruding portion of the first metal layer pattern; and

forming a lower wire comprising the second conductive layer pattern and a second metal layer pattern, the second metal layer pattern being dividedly formed by etching the first metal layer pattern with the use of the spacer.

2. The method of claim 1 , wherein the conductive layer pattern has a higher hardness than the metal layer pattern and high etch selectivity with respect to the metal layer pattern.

3. The method of claim 2 , wherein the conductive layer pattern comprises a polysilicon layer pattern.

4. The method of claim 1 , wherein the hole of the first conductive layer pattern has a critical dimension of about 50% of that of the mask pattern.

5. The method of claim 1 , wherein forming the first metal layer pattern comprises partially etching the metal layer to about 50 to 60% of the total thickness of the metal layer.

6. The method of claim 1 , wherein the spacer comprises an oxide layer.

7. The method of claim 1 , wherein forming the lower wire comprises etching the first metal layer pattern using a gas plasma including Cl under a power of 100 to 300 W and a pressure of 5 to 20 mTorr.

8. The method of claim 6 , wherein forming the lower wire comprises etching the first metal layer pattern using a gas plasma including Cl under a power of 100 to 300 W and a pressure of 5 to 20 mTorr.

9. The method of claim 1 , further comprising, after forming the lower wire:

removing the spacer;

forming an upper interlayer insulating layer on the lower interlayer insulating layer in order to cover the lower wire; and

forming a via hole by etching the upper interlayer insulating layer to expose the lower wire.

10. The method of claim 1 , further comprising, after forming the lower wire:

forming an upper interlayer insulating layer on the lower interlayer insulating layer in order to cover the lower wire and the spacer; and

forming a via hole by etching the upper interlayer insulating layer to expose the lower wire, and removing the spacer while etching the upper interlayer insulating layer.

11. The method of claim 9 , wherein etching the upper interlayer insulating layer comprises main etching and over-etching.

12. The method of claim 10 , wherein etching upper interlayer insulating layer comprises two steps, a main etching step and an over-etching step.

13. The method of claim 11 , wherein the main etching comprises using a gas plasma including F under a power of 1000 to 2000 W and a pressure of 50 to 100 mTorr, and the over-etching comprises using a gas plasma including F under a power of 100 to 500 W and a pressure of 100 to 500 mTorr.

14. The method of claim 12 , wherein the main etching step comprises using a gas plasma including F under a power of 1000 to 2000 W and a pressure of 50 to 100 mTorr, and to over-etching step comprises using a gas plasma including F under a power of 100 to 500 W and a pressure of 100 to 500 mTorr.

15. The method of claim 1 , wherein the metal layer comprises a metal selected from the group consisting of Al, Al—Cu alloy, Cu, W, Pt, Au, Ti, TiN, and TiW.

16. The method of claim 1 , wherein forming the spacer comprises depositing an oxide layer to a thickness of about 1000 Å over the second conductive layer pattern and the first metal layer pattern, and etching the oxide layer using a gas plasma comprising a fluorine-containing gas at a flow rate of about 50 to about 200 sccm and a pressure of about 100 to about 500 mTorr, and a power of about 1000 to about 2000 W.

17. The method of claim 1 , wherein the second conductive layer pattern retains the hole of the first conductive layer pattern and has a ring-like shape having a diameter of about twice a diameter of the hole.

18. The method of claim 7 , further comprising forming an upper wire in the via hole electrically connected to the lower wire including the second conductive layer pattern and a second metal layer pattern.

19. The method of claim 1 , wherein the protruding portion of the first metal layer pattern has a round, column-like shape, a height of about 50% to about 60% the thickness of the metal layer, and a width of about twice a diameter of the hole of the first conductive layer pattern.

20. A method of forming an interconnection line of a semiconductor device, comprising:

forming a metal layer on a semiconductor substrate including a lower interlayer insulating layer;

forming a conductive layer on the metal layer;

etching the first conductive layer to form a first conductive pattern including a hole to partially expose the metal layer;

forming a mask pattern in the hole and over the first conductive pattern that masks the first conductive pattern around the hole;

etching the first conductive pattern and the metal layer up to a predetermined thickness using the mask pattern as a mask to form a second conductive pattern comprising portions of the etched first conductive pattern and the etched metal layer;

removing the mask pattern;

forming spacers on sidewalls of the second conductive pattern, including the etched first conductive pattern and the etched metal layer; and

etching the second conductive pattern using the spacers as a mask to form a lower wire having a step-like profile.