Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same
View Patent ↗Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type. A collector region of the second conductivity type is formed on the ground surface of the semiconductor substrate of the FS region, thereby forming an FS-IGBT.
1. A method of manufacturing a power semiconductor device, the method comprising:
preparing a semiconductor substrate having a constant concentration profile of a first conductivity type impurities in a depth direction;
growing an epitaxial layer on one surface of the semiconductor substrate, the epitaxial layer being doped at a concentration lower than that of the semiconductor substrate and being intended to be used as a drift region;
forming a base region of a second conductivity type in a predetermined region of the epitaxial layer;
forming an emitter region of the first conductivity type in a predetermined region of the base region;
forming a gate electrode with a gate insulating layer on the base region between the emitter region and the drift region of the epitaxial layer;
forming an emitter electrode contacting with the base region and the emitter region;
grinding a rear surface of the semiconductor substrate opposite the gate electrode to reduce the thickness of the semiconductor substrate, thereby setting an FS (field stop) region having a constant concentration profile of the first conductivity type impurities in a depth direction, wherein there is no need for ion-implantation and thermal treatment in order to form the field stop region; and
forming a collector region of the second conductivity type on the ground surface of the semiconductor substrate of the FS region.
2. The method of claim 1 , wherein the semiconductor substrate is an N 0 semiconductor substrate doped with the N-type impurities at a concentration of 1E15/cm 3 to 2E16/cm 3 .
3. The method of claim 2 , wherein the FS region is set to a portion of the N 0 semiconductor substrate remaining after the grinding, thereby having a constant concentration profile in the depth direction.
4. The method of claim 1 , wherein the forming of the base region includes:
selectively ion-implanting impurities of the second conductivity type into a surface of the epitaxial layer; and
diffusing the ion-implanted impurities.
5. The method of claim 1 , wherein the forming of the emitter region includes:
selectively ion-implanting impurities of the first conductivity type into a surface of the base region; and
diffusing the ion-implanted impurities.
6. The method of claim 1 , wherein the collector region is formed to a constant depth below the ground surface of the remaining semiconductor substrate by ion implantation.
7. The method of claim 1 , wherein the forming of the collector region includes:
ion-implanting impurities of the second conductivity type into the ground surface of the semiconductor substrate; and
performing a thermal treatment process on the ion-implanted impurities.
8. The method of claim 1 , further comprising:
forming an emitter electrode electrically connected to the emitter region; and
forming a collector electrode electrically connected to the collector region.
9. The method of claim 1 , wherein the FS region has a doping concentration lower than the collector region and greater than the drift region.