Power core devices and methods of making thereof
The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.
1. A device having a semiconductor device with power terminals mounted thereon, and having a power core incorporated therein, said power core comprising:
a planar capacitor laminate;
a layer of a prepreg; and
a surface mount technology (SMT) discrete chip capacitor embedded in said prepreg layer, wherein said embedded surface mount technology (SMT) discrete chip capacitor is encapsulated within said prepreg layer, and wherein said surface mount technology (SMT) discrete chip capacitor comprises at least a first electrode and a second electrode;
wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said surface mount technology (SMT) discrete chip capacitor;
wherein said embedded surface mount technology (SMT) discrete chip capacitor is connected in parallel to said planar capacitor laminate, and wherein said first electrode and second electrode of said surface mount technology (SMT) discrete chip capacitor are connected to at least one power terminal of the semiconductor device; and
wherein said embedded surface mount technology (SMT) discrete chip capacitor is closer to power terminals of the semiconductor device than is said planar capacitor laminate.
2. The power core of claim 1 wherein said planar capacitor laminate comprises a ceramic dielectric layer.
3. The device of claim 1 wherein the semiconductor device is an integrated circuit.
4. The device of claim 1 comprising more than one signal layer wherein said signal layers are connected through conductive vias.
5. The device of claim 1 wherein said device is selected from an interposer, printed wiring board, multichip module, area array package, system-on-package, and system-in-package.
6. The device of claim 1 wherein said planar capacitor laminate comprises an organic layer dielectric layer.
7. The device of claim 6 wherein said planar capacitor laminate comprises a ceramic material filled organic dielectric layer, wherein the ceramic material of said layer has a dielectric constant of greater than 500.
8. The device of claim 1 wherein said planar capacitor laminate is a copper-dielectric-copper laminate.
9. The device of claim 8 wherein said copper-dielectric-copper laminate comprises one or more dielectric layers selected from an organic layer, a ceramic-filled organic layer, a ceramic layer, and mixtures thereof.
10. The device of claim 1 wherein the prepreg is an epoxy or a polymer resin.
11. The device of claim 1 wherein an additional circuit layer is laminated over the prepreg layer encapsulating the surface mount technology (SMT) discrete chip capacitor.
12. The device of claim 1 comprising more than one surface mount technology (SMT) discrete chip capacitor embedded in and encapsulated within said prepreg layer, wherein each of said surface mount technology (SMT) discrete chip capacitors:
comprises at least a first electrode and a second electrode, and said first electrode and second electrode of each said surface mount technology (SMT) discrete chip capacitor is connected to at least one power terminal of the semiconductor device;
is connected in parallel to said planar capacitor laminate such that said planar capacitor laminate serves as a low inductance path to supply a charge to said embedded surface mount technology (SMT) discrete chip capacitor; and
is closer to power terminals of the semiconductor device than is said planar capacitor laminate to which said surface mount technology (SMT) discrete chip capacitor is connected in parallel.