Semiconductor integrated device, method of designing semiconductor integrated device, device for designing the same, and program

1. A semiconductor integrated device having a plurality of wires, comprising:

a minimum wiring space between a first plurality of wires disposed in a first wiring layer in a first location is defined as SL 1 , where each of the first plurality of wires disposed in the first location are fine wires and all wires in the first location are disposed at the first wiring layer,

a minimum wiring space between a second plurality of wires disposed in a second wiring layer in a second location is defined as SL 2 , where at least one of the second plurality of wires disposed in the second location is a wide wire and neighboring wires with respect to the at least one of the second plurality of wires are at an equal voltage potential and all wires in the second location are disposed at the second wiring layer, and

a minimum wiring space between a third plurality of wires disposed in a third wiring layer in a third location is defined as SL 3 , where at least one of the third plurality of wires disposed in the third location is a wide wire and all neighboring wires with respect to the at least one of the third plurality of wires are fine wires and are at an unequal voltage potential with respect to the wide wire in the third location and all wires in the third location are disposed at the third wiring layer,

wherein said semiconductor integrated device has a wire layout structure such that SL 1 ≦SL 2 <SL 3 .

2. The semiconductor integrated device as defined by claim 1 wherein, for a plurality of vias that connect wires between different wiring layers,

a minimum space between vias in an area other than a via-dense area is SV 1 ,

a minimum space between vias at a substantially equal voltage potential with respect to each other in a via-dense area is SV 2 , and

a minimum space between vias at a substantially unequal voltage potential with respect to each other in a via-dense area is SV 3 ,

wherein said semiconductor integrated device has a layout structure such that SV 1 ≦SV 2 <SV 3 .

3. The semiconductor integrated device as defined by claim 1 wherein said wide wire includes a power wire.

4. A wiring method for laying out wiring of a semiconductor integrated device using a design device, said wiring method comprising the steps of:

wiring wires, by using a computer, at a minimum wiring space SL 1 between a first plurality of wires disposed in a first wiring layer in a first location where each of the first plurality of wires disposed in the first location are fine wires and all wires in the first location are disposed at the first wiring layer;

wiring wires at a minimum wiring space SL 2 between a second plurality of wires disposed in a second wiring layer in a second location where at least one of the second plurality of wires disposed in the second location is a wide wire and neighboring wires with respect to the at least one of the second plurality of wires are at an equal voltage potential and all wires in the second location are disposed at the second wiring layer; and

wiring wires at a minimum wiring space SL 3 between a third plurality of wires disposed in a third wiring layer in a third location where the neighboring at least one of the third plurality of wires disposed in the third location is a wide wire and is at an unequal voltage potential with respect to all neighboring wires of the third plurality of wires, the all neighboring wires of the third plurality of wires being fine wires and all wires in the third location are disposed at the third wiring layer, where SL 1 ≦SL 2 <SL 3 .

5. A computer readable medium storing a computer program for causing a computer that constitutes a design device for laying out wiring of a semiconductor integrated device to perform the following steps comprising:

wiring wires at a minimum wiring space SL 1 between a first plurality of wires disposed in a first wiring layer in a first location where each of the first plurality of wires disposed in the first location are fine wires and all wires in the first location are disposed at the first wiring layer;

wiring wires at a minimum wiring space SL 2 between a second plurality of wires disposed in a second wiring layer in a second location where at least one of the second plurality of wires disposed in the second location is a wide wire and neighboring wires with respect to the at least one of the second plurality of wires are at an equal voltage potential and all wires in the second location are disposed at the second wiring layer; and

wiring wires at a minimum wiring space SL 3 between a third plurality of wires disposed in a third wiring layer in a third location where the neighboring at least one of the third plurality of wires disposed in the third location is a wide wire and is at an unequal voltage potential with respect to all neighboring wires of the third plurality of wires, the all neighboring wires of the third plurality of wires being fine wires and all wires in the third location are disposed at the third wiring layer, where SL 1 ≦SL 2 <SL 3 .