Storage electrode of a capacitor and a method of forming the same
In an embodiment, a storage electrode of a capacitor in a semiconductor device is resistant to inadvertent etching during its manufacturing processes. A method of forming the storage electrode of the capacitor is described. The storage electrode of the capacitor may include a first metal layer electrically connected with a source region of a transistor through a contact plug penetrating an insulating layer on a semiconductor substrate. A polysilicon layer may then be formed on the first metal layer. A second metal layer is formed on the polysilicon layer.
1. A method of forming a semiconductor device including a capacitor comprising:
patterning a mold layer formed on an insulating layer on a semiconductor substrate, thereby forming a storage electrode hole exposing an upper portion of a contact plug that penetrates the insulating layer;
forming a first metal layer over the resulting structure including the storage electrode hole;
forming an amorphous silicon layer on the first metal layer;
forming a second metal layer on the amorphous silicon layer, thereby forming a storage electrode layer; and
annealing the storage electrode layer to crystallize the amorphous silicon layer.
2. The method according to claim 1 , wherein the mold layer is formed by sequentially forming a lower mold layer, an etch stop layer, and an upper mold layer on the insulating layer that includes the contact plug.
3. The method according to claim 1 , further comprising, after forming the storage electrode layer and before the wet etch process:
forming a sacrificial oxide layer on the storage electrode layer; and
planarizing and etching the sacrificial oxide layer and the storage electrode layer until the mold layer is exposed.
4. The method according to claim 3 , wherein, after the planarizing and etching, the remaining sacrificial oxide layer is removed using a wet etch process.
5. A method of forming a semiconductor device including a storage electrode of a capacitor comprising:
forming a contact plug penetrating an insulating layer on a semiconductor substrate;
sequentially forming a lower mold layer, an etch stop layer, and an upper mold layer on the insulating layer including the contact plug;
sequentially patterning the upper mold layer, the etch stop layer, and the lower mold layer, thereby forming a storage electrode hole that exposes an upper portion of the contact plug; sequentially forming a first metal layer, an amorphous silicon layer, and a second metal layer on the resulting structure including the storage electrode hole, thereby forming a storage electrode layer;
forming a sacrificial layer on the storage electrode layer;
planarizing the sacrificial layer and the storage electrode layer until the upper mold layer is exposed;
removing the sacrificial oxide layer remaining after the planarizing;
isotropically etching the upper mold layer, thereby exposing the etch stop layer and concurrently, exposing an outer wall of the storage electrode layer to form a storage electrode; and annealing the storage electrode to crystallize the amorphous silicon layer.
6. The method according to claim 5 , wherein the storage electrode has a concave shape.
7. The method according to claim 5 , wherein the amorphous silicon layer is deposited at a temperature of about 530° C. or less.
8. The method according to claim 5 , wherein the amorphous silicon layer is formed by thermally decomposing silane (SiH 4 ) gas.
9. The method according to claim 5 , wherein the sacrificial layer is removed by a wet etch process, using an LAL etch solution.
10. The method according to claim 5 , wherein the annealing of the storage electrode to crystallize the amorphous silicon layer is performed at a temperature of about 550° C. to about 600° C.
11. The method according to claim 5 , wherein the storage electrode sequentially includes a first titanium nitride layer, a polysilicon layer, and a second titanium nitride layer.
12. A method of forming a semiconductor device including a capacitor comprising:
patterning a mold layer formed on an insulating layer on a semiconductor substrate, thereby forming a storage electrode hole extending through the mold layer;
forming a first metal layer over the resulting structure including the storage electrode hole;
forming a silicon layer on the first metal layer; and
forming a second metal layer on the silicon layer, thereby forming a storage electrode layer,
wherein forming the silicon layer comprises depositing an amorphous silicon layer at a temperature of about 530° C. or less and annealing the resulting structure at a temperature of about 550° C.to about 600° C.
13. The method according to claim 12 , wherein the first metal layer comprises titanium nitride.
14. The method according to claim 12 , wherein forming the second metal layer comprises forming the second metal layer directly on the silicon layer.
15. The method according to claim 14 , wherein forming the silicon layer comprises forming the silicon layer directly on the first metal layer.