IP Library Granted Patent US 7,288,990
Granted Patent B2
US 7,288,990 · App. 11/292,116 · Granted Oct 30, 2007

Reference buffer with dynamic current control

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Quick Facts
Patent No.
US 7,288,990
App. No.
11/292,116
Granted
Oct 30, 2007
Kind
B2
Abstract

A method can allow a system to selectively control increasing of a bias source in a reference buffer or decreasing impedance looking into a output of the reference buffer for a temporary or selective time period, which can result in an increased overall efficiency of the system. The method can include at least the following steps. A first input signal is received at an input of a reference buffer. A second input signal is received from a load at an output of the reference buffer. A value of a bias source coupled to the output of the reference buffer is modulated, such that a spike of a signal at the output of the reference buffer caused by the second input signal is maintained below a threshold value. Alternatively, an impedance looking into the output of the reference buffer is modulated, such that a spike of a signal at the output of the reference buffer caused by the second input signal is maintained below a threshold value.

Claims (45)

1. A method comprising:

(a) receiving a first input signal at an input of a reference buffer;

(b) receiving a second input signal from a load at an output of the reference buffer; and

(c) controlling a bias source using a control device so as to modulate a value of the bias source coupled to the output of the reference buffer or an impedance looking into the output of the reference buffer, such that a spike of a value at the output of the reference buffer caused by step (b) is maintained below a threshold value.

2. The method of claim 1 , wherein the load comprises a temporally varying load.

3. The method of claim 1 , wherein the load comprises a switched capacitor load.

4. The method of claim 1 , wherein step (c) comprises temporarily increasing the value of the bias source so as to temporarily reduce the impedance looking into the output of the reference buffer.

5. The method of claim 1 , wherein:

the second input signal varies during first and second phases of operation of the load; and

the modulating step begins at the end of one of the first and second phases and ends during another one of the first and second phases.

6. The method of claim 1 , wherein step (a) comprises using one of a constant single-ended input signal and a constant differential input signal as the first input signal.

7. The method of claim 1 , further comprising coupling the bias source to the output of the reference buffer from a location within the reference buffer.

8. The method of claim 1 , wherein step (c) comprises using a control device located outside of the bias source.

9. A system comprising:

a reference buffer having an input and an output;

a bias source coupled to the output;

a control device coupled to the bias source; and

a load coupled to the output,

wherein receiving charge from the load at the output causes a spike at the output and wherein the control device modulates the bias source so that the spike is maintained below a threshold value.

10. The system of claim 9 , wherein the bias source is a current source.

11. The system of claim 9 , wherein the control device is a register.

12. The system of claim 9 , wherein the bias source is positioned within the reference buffer.

13. The system of claim 9 , wherein:

the receiving charge varies during first and second phases of operation of the load; and

the modulating begins at the completion of one of the first and second phases and ends during another one of the first and second phases.

14. The system of claim 9 , wherein the bias source is coupled to the output of the reference buffer from a location within the reference buffer.

15. The system of claim 9 , wherein the control device is located outside of the bias source.

16. A method comprising:

(a) receiving a first input signal at a first input of a reference buffer;

(b) receiving a second input signal from a load at a first differential output of the reference buffer;

(c) receiving a third input signal from the load at a second differential output of the reference buffer;

(d) coupling a first bias source to the first differential output of the reference buffer from a location within the reference buffer;

(e) coupling a second bias source to the second differential output of the reference buffer from a location within the reference buffer; and

(f) controlling the first and second bias sources using a control device so as to modulate respective values of the first and second bias sources, such that a spike of a value at the first differential output of the reference buffer caused by step (b) is maintained below a threshold value.

17. The method of claim 16 , wherein the controlling steps begin at the end of one of the first and second phases and ends during another one of the first and second phases.

18. A system comprising:

a reference buffer having an input and first and second differential outputs;

a first bias source located within the reference buffer and coupled to the first differential output;

a second bias source located within the reference buffer and coupled to the second differential output;

a first control device coupled to the first bias source;

a second control device coupled to the second bias source; and

a load coupled to the differential outputs,

wherein receiving charge from the load at the first differential output causes a spike at the first differential output, and

wherein the first and second control devices modulate the first and second bias sources respectively so that the spike is maintained below a threshold value.

19. The system of claim 18 , wherein the modulating begins at the end of one of the first and second phases and ends during another one of the first and second phases.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2007
From: RANGANATHAN, SUMANT
To: BROADCOM CORPORATION
Reel/Frame 019081/0129 →