Method of forming a gate pattern in a semiconductor device

1. A gate pattern in a semiconductor device, comprising:

a semiconductor wafer;

a gate oxide layer on the semiconductor wafer;

an overetched gate electrode pattern on the gate oxide layer;

an anti-reflection coating pattern on the gate electrode layer; and

an ArF photoresist pattern on the anti-reflection coating pattern, coextensive with the anti-reflection coating pattern.

2. The gate pattern of claim 1 , wherein the gate pattern has a critical dimension of 60-70 nm.

3. The gate pattern of claim 2 , wherein the photoresist pattern has a critical dimension of 100-110 nm.

4. The gate pattern of claim 1 , wherein the gate oxide layer has a thickness of 10-20 Å, the gate electrode pattern has a thickness of 1500-1800 Å, the anti-reflection coating pattern has a thickness of 300-400 Å, and the ArF photoresist pattern has a thickness of 2000-2700 Å.

5. A method of forming a gate pattern in a semiconductor device, comprising:

sequentially forming a gate oxide layer, a gate electrode layer, an anti-reflection coating layer, and an ArF photoresist layer on a semiconductor wafer;

forming a photoresist pattern by exposing and developing the ArF photoresist layer;

etching the anti-reflection coating layer using the photoresist pattern as an etching mask;

removing an oxide layer formed during etching of the anti-reflection coating layer;

etching the gate electrode layer; and

over-etching a remaining gate electrode layer.

6. The method of claim 5 , wherein a critical dimension of the photoresist pattern before etching is 100-110 nm.

7. The method of claim 5 , wherein etching the anti-reflection coating layer, removing the oxide layer, etching the gate electrode layer, and over-etching a remaining gate electrode layer each comprise etching with an inductively coupled plasma (ICP).

8. The method of claim 5 , wherein the gate oxide layer has a thickness of 10-20 Å.

9. The method of claim 5 , wherein the gate electrode layer has a thickness of 1500-1800 Å.

10. The method of claim 5 , wherein the anti-reflection coating layer has a thickness of 300-400 Å.

11. The method of claim 5 , wherein the ArF photoresist layer has a thickness of 2000-2700 Å.

12. The method of claim 5 , wherein the gate oxide layer has a thickness of 10-20 Å, the gate electrode layer has a thickness of 1500-1800 Å, the anti-reflection coating layer has a thickness of 300-400 Å, and the ArF photoresist layer has a thickness of 2000-2700 Å.

13. The method of claim 7 , wherein etching the anti-reflection coating layer further comprises flowing an etching gas comprising a fluorocarbon and an oxygen source at a rate of 80-130 sccm, and maintaining a chamber pressure of 0.5-25 mTorr, a source power of 100-1000 W, and a bias power of 5-100 W; and the method further comprises:

detecting an end-point of etching the anti-reflection coating layer; and

over-etching the remaining anti-reflection coating layer.

14. The method of claim 7 , wherein etching the anti-reflection coating layer further comprises flowing an etching gas comprising CF 4 and O 2 at a rate of from 80 to 130 sccm, maintaining a pressure of an etching chamber at a level of 1-10 mTorr, maintaining a source power at 200-500 W, and maintaining a bias power at 10-70 W, and the method further comprises an additional over-etching process, performed after detecting an end-point of the etching.

15. The method of claim 7 , wherein removing the oxide layer further comprises etching with a gas comprising a fluorocarbon having a flow rate of 20-100 sccm, for a time of 2-20 sec, and at a pressure of 0.5-10 mTorr, a source power of 100-1000 W, and a bias power of 10-100 W.

16. The method of claim 7 , wherein removing the oxide layer comprises etching with a gas comprising CF 4 flowed at a rate of 40-60 sccm, for a process time of 5-10 sec, a pressure of 1-7 mTorr, a source power of 300-700 W, and a bias power of 20-70 W.

17. The method of claim 7 , wherein etching the gate electrode layer comprises etching with a gas comprising a chlorine source, a hydrogen halide and (optionally) an oxygen source having a total flow rate of 100-250 sccm, for a time of 10-100 sec, and at a chamber pressure of 0.5-10 mTorr, a source power of 200-1000 W, and a bias power of 20-200 W.

18. The method of claim 7 , wherein etching the gate electrode layer comprises etching with a gas comprising Cl 2 flowed at a rate of 10-50 sccm, HBr flowed at a rate of 100-180 sccm, and O 2 flowed at a rate of 0-5 sccm, for a process time of 30-50 sec, and at a chamber pressure of 1-7 mTorr, a source power of 300-800 W, and a bias power of 50-100 W.

19. The method of claim 7 , wherein over-etching the remaining gate electrode layer comprises etching with a gas comprising a nitrogen source, a hydrogen halide and an oxygen source having a flow rate of 100-250 sccm, for a time of 60-240 sec, and at a pressure of 10-150 mTorr, a source power of 500-2500 W, and a bias power of 20-500 W.

20. The method of claim 7 , wherein over-etching the remaining gate electrode layer comprises etching with a gas comprising N 2 flowed at a rate of 5-15 sccm, HBr flowed at a rate of 130-170 sccm, and O 2 flowed at a rate of 1-5 sccm, for a process time of 100-140 sec, and at an etching chamber pressure of 50-100 mTorr, a source power of 700-1500 W, and a bias power of 50-200 W.