IP Library Granted Patent US 7,427,561
Granted Patent B2
US 7,427,561 · App. 11/293,081 · Granted Sep 23, 2008

Method for manufacturing semiconductor device

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Quick Facts
Patent No.
US 7,427,561
App. No.
11/293,081
Granted
Sep 23, 2008
Kind
B2
Abstract

A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; forming a source/drain region in a surface of the semiconductor substrate at either side of the gate electrode; forming a metal layer on the surface of the semiconductor substrate including the gate electrode; performing a plasma treatment on the metal layer; forming a capping material layer on the metal layer; performing an annealing process upon the semiconductor substrate, to form a metal silicide layer on the surface of the semiconductor substrate at positions corresponding to the gate electrode and the source/drain region; and removing the capping material layer and the metal layer remained without reaction with the gate electrode and the semiconductor substrate.

Claims (14)

1. A method for manufacturing a semiconductor device, comprising:

forming a gate electrode on a semiconductor substrate by interposing a gate insulation layer;

forming an insulation side wall at either lateral surface of the gate electrode;

forming a source/drain region in a surface of the semiconductor substrate at either side of the gate electrode;

forming a metal layer on the surface of the semiconductor substrate including the gate electrode;

performing a plasma treatment on the metal layer;

forming a capping material layer on the metal layer using one of physical vapor deposition and chemical vapor deposition;

performing an annealing process upon the semiconductor substrate to form a metal silicide layer on the surface of the semiconductor substrate at positions corresponding to the gate electrode and the source/drain region; and

removing the capping material layer and the metal layer left unreacted with the gate electrode and the semiconductor substrate;

wherein the forming of the metal layer, the plasma treatment, the forming of the capping material layer, and the annealing process are performed in the same chamber via an in-situ process.

2. The method as set forth in claim 1 , wherein the plasma treatment is performed using nitrogen or ammonia gas.

3. The method as set forth in claim 1 , wherein the annealing process is performed under nitrogen or ammonia atmosphere.

4. The method as set forth in claim 1 , wherein the capping material layer is formed by depositing one of a titanium layer, a nitride titanium layer, and a titanium/nitride titanium layer.

5. The method as set forth in claim 1 , wherein the metal layer is selected from the group consisting of a nickel layer, a cobalt layer, a titanium layer, a tungsten layer, a tantalum layer, and a molybdenum layer.

Assignments (2)
CHANGE OF NAME Recorded Jun 15, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018176/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2005
From: LEE, HAN CHOON
To: DONGBUANAM SEMICONDUCTOR, INC.
Reel/Frame 017326/0288 →