IP Library Granted Patent US 7,330,146
Granted Patent B2
US 7,330,146 · App. 11/293,263 · Granted Feb 12, 2008

Minimized SAR-type column-wide ADC for image sensors

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Quick Facts
Patent No.
US 7,330,146
App. No.
11/293,263
Granted
Feb 12, 2008
Kind
B2
Abstract

An improved analog-to-digital converter wherein a minimal amount of circuitry is provided for conversion of an analog signal to a series of digital bits. A comparator is provided for generating digital values to which the digital bits correspond. A digital-to-analog converter is provided for generating, via successive approximation, a feedback analog signal based on bits previously generated by the comparator. The analog-to-digital converter compares the feedback analog signal to the input analog signal, and based on the comparison generates a digital value that corresponds to a digital bit. In the method of the invention, an analog signal is converted to a digital value using the analog-to-digital converter, and a digital-to-analog converter comprising two capacitors and a reference selector generates, via successive approximation, a feedback analog signal that is applied to a comparator for comparison to the input analog signal being digitized.

Claims (24)

1. A method for generating a digital-to-analog converter reset voltage, for a digital-to-analog converter, said method comprising:

generating a first analog reference voltage;

applying said first analog reference voltage to a second capacitor of said digital-to-analog converter;

generating a second analog reference voltage;

applying said second analog reference voltage to a first capacitor of said digital-to-analog converter;

charge sharing said first capacitor and second capacitor to generate an analog reset voltage.

2. The method for generating a digital-to-analog converter reset voltage of claim 1 , wherein said digital-to-analog converter further comprises a reference selector for generating and applying each said first analog reference voltage and said second analog reference voltage.

3. The method of generating a digital-to-analog converter reset voltage of claim 2 , wherein a first control signal is applied to said reference selector for generating said first analog reference voltage, and wherein a second control signal is applied to said reference selector for generating said second analog reference voltage.

4. A method for generating a digital-to-analog converter reset voltage for a digital-to-analog converter, said method comprising:

generating a first analog reference voltage;

applying said first analog reference voltage to a second capacitor of said digital-to-analog converter;

generating a second analog reference voltage;

applying said second analog reference voltage to a first capacitor of said digital-to-analog converter;

charge sharing said first capacitor and second capacitor to generate an analog reset voltage;

wherein said digital-to-analog converter comprises:

a reference selector for generating and applying each said first analog reference voltage and said second analog reference voltage, and

a first switch for coupling said reference selector to said first capacitor and second capacitor; and a second switch for coupling said second capacitor and a feedback output line to said first capacitor and said reference selector;

wherein said first switch is closed and said second switch is closed during said step of applying said first analog reference voltage,

said first switch is closed and said second switch is open during said step of applying said second analog reference voltage, and

said first switch is open, and said second switch is closed during said step of charge sharing.

5. The method for generating a digital-to-analog conversion reset voltage of claim 4 , further comprising the step of generating a most significant bit of a N-bit series, comprising:

applying said analog reset voltage to an operational amplifier;

applying a first analog input signal to said operational amplifier; and

comparing said first analog input signal to said analog reset voltage, and outputting a digital amplifier output signal based on the results of said comparing.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: MICRON TECHNOLOGY, INC.
To: APTINA IMAGING CORPORATION
Reel/Frame 040823/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2016
From: BOEMLER, CHRISTIAN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040402/0269 →