IP Library Granted Patent US 7,446,682
Granted Patent B2
US 7,446,682 · App. 11/293,416 · Granted Nov 4, 2008

Analog to digital converter with distortion correction

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Quick Facts
Patent No.
US 7,446,682
App. No.
11/293,416
Granted
Nov 4, 2008
Kind
B2
Abstract

A system and method are disclosed for correcting for output distortion of an analog to digital converter, comprising: estimating the output distortion, providing an estimated distortion, and combining an output of the analog to digital converter with the estimated distortion to compensate for the output distortion. The compensating module for correcting output distortion of an analog to digital converter comprises a calibration module configured to estimate the output distortion and a combiner configured to combine an output of the analog to digital converter with the estimated distortion to compensate the output distortion.

Claims (31)

1. A method of correcting for output distortion of an analog to digital converter (ADC) having an output that includes a plurality of output bits, comprising:

estimating the output distortion to obtain an estimated distortion, wherein:

the plurality of output bits include a plurality of higher order bits and at least one lower order bit;

the estimation is based at least in part on the plurality of higher order bits of the output but is not based on the at least one lower order bit;

combining the output of the ADC with the estimated distortion to compensate for the output distortion; and

training a calibration module; wherein

the calibration module includes a plurality of linear filters having a plurality of coefficients, and wherein

training the calibration module includes sending the output to the calibration module and feeding back an error adaptation signal to adapt the plurality of coefficients.

2. A method as recited in claim 1 , further comprising training a calibration module.

3. A method as recited in claim 2 , further comprising disconnecting an adaptation path after training.

4. A method as recited in claim 2 , wherein the calibration module is trained to model a distortion function of the ADC.

5. A method as recited in claim 2 , wherein the calibration module is trained to model a distortion function of the ADC, the distortion function being a nonlinear function of at least some of the plurality of higher order bits of the ADC.

6. A method as recited in claim 2 , wherein training the calibration module includes sending the output to the calibration module and feeding back an error adaptation signal to adapt the calibration module.

7. A method as recited in claim 1 , wherein estimating the output distortion includes determining interference effect of one or more higher order bits of the output on one or more lower order bits of the output.

8. A method of correcting for output distortion of an analog to digital converter (ADC) having an output that includes a plurality of output bits that includes a plurality of higher order bits and at least one lower order bit, comprising:

estimating the output distortion to obtain an estimated distortion, wherein estimation of the output distortion is based at least in part on at least some of the plurality of higher order bits of the output but is not based on the at least one lower order bit, and the estimation includes performing a nonlinear operation that is equivalent to an absolute value operation that operates on at least some of the plurality of higher order bits but does not operate on the at least one lower order bit; and

combining the output of the ADC with the estimated distortion to compensate for the output distortion.

9. A distortion correcting analog to digital converter system comprising:

an analog to digital converter (ADC) having an output with an output distortion, the output comprising a plurality of output bits including a plurality of higher order bits and at least one lower order bit; and

a calibration module coupled to the ADC, configured to estimate the output distortion to obtain an estimated distortion, wherein the estimated distortion is based at least in part on the plurality of higher order bits of the output but is not based on the at least one lower order bit;

wherein the calibration module includes a plurality of linear filters having a plurality of coefficients, and wherein the calibration module is configured to be trained, including by sending the output to the calibration module and feeding back an error adaptation signal to adapt the plurality of coefficients.

10. A system as recited in claim 9 , wherein the calibration module is configured to be trainable.

11. A system as recited in claim 10 , wherein the calibration module is further configured to disconnect an adaptation path after training.

12. A system as recited in claim 10 , wherein the calibration module is trained to model a distortion function of the ADC.

13. A system as recited in claim 10 , wherein the calibration module is trained to model a distortion function of the ADC, the distortion function being a nonlinear function of one or more of the plurality of higher order bits.

14. A system as recited in claim 10 , wherein the calibration module is trained, including by sending the output to the calibration module and feeding back an error adaptation signal to adapt the calibration module.

15. A distortion correcting analog to digital converter system comprising:

an analog to digital converter (ADC) having an output with an output distortion, the output comprising a plurality of output bits that includes a plurality of higher order bits and at least one lower order bit; and

a calibration module coupled to the ADC, configured to estimate the output distortion to obtain an estimated distortion, wherein the estimated distortion is based at least in part on at least some of the plurality of higher order bits but is not based on the at least one lower order bit;

wherein the calibration module estimates the output distortion, including by performing a nonlinear operation that is equivalent to an absolute value operation that operates on at least some of the plurality of higher order bits but does not operate on the at least one lower order bit.

16. A system as recited in claim 9 , wherein to estimate the output distortion includes to determine interference effect of one or more higher order bits of the output on one or more lower order bits of the output.

Assignments (7)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: OPTICHRON, INC.
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 026592/0811 →
SECURITY AGREEMENT Recorded Dec 1, 2010
From: OPTICHRON, INC.
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 025434/0718 →