Semiconductor memory device with adjustable I/O bandwidth

1. A memory device, comprising:

a plurality of data I/O buffers connected one by one to a plurality of I/O ports for inputting/outputting a plurality of data bits;

a switch array comprising a plurality of switches for delivering data between a data bus and the plurality of data I/O buffers to process the data by an adjustable number of data bits; and

a switch controller for controlling activation of the plurality of data I/O data buffers and on/off operations of the plurality of switches in response to external control signals and outputs of a column decoder, wherein the switch controller receives one of the external control signals via one of the data I/O ports.

2. A memory device, comprising:

buffer means for receiving and outputting a plurality of data bits in response to a buffer control signal, the buffer means coupled to a plurality of data I/O pin means for providing electrical connections to external circuits;

sense means for sensing and amplifying a plurality of data bits delivered through a data bus, wherein the sense means is controlled by outputs of a column decoding means;

switch means for connecting the buffer means to the sense means in response to a switch control signal; and

control means for receiving external control signals and the outputs of the column deco ding means, wherein at least one of the external control signals and the outputs of the column decoding signals is received via one or more of the plurality of the data I/O pins, for controlling the buffer means by providing the buffer control signal, and for controlling the switch means by providing the switch control signal

3. The memory device according to claim 1 , further comprising:

a sense amplifier array for detecting and amplifying the data delivered through the data bus to transfer the data into the switch array, wherein the sense amplifier is controlled by the outputs of the column decoder.

4. The memory device according to claim 1 , further comprising:

a plurality of cell array blocks for storing the data; and

a plurality of column selection controllers for selectively delivering the data between the plurality of cell array blocks and the data bus.

5. The memory device according to claim 3 , wherein the memory device is a ferroelectric memory device having a bitline structure comprising:

a main bitline;

a plurality of sub bitlines;

a main bitline load controller for controlling impedance between the main bitline and a power voltage source according to a first control signal;

a main bitline pull-up controller for providing a voltage to the main bitline according to a second control signal, wherein the main bitline pull-up controller is in an active state during a precharge operation; and

a current controller for controlling a current flowing from the main bitline to a ground according to a sensing voltage of one sub bitline of the plurality of the sub bitlines to induce a sensing voltage of the main bitline according to the current.

6. The memory device according to claim 2 , wherein the memory device is a ferroelectric memory device having a bitline structure comprising:

a main bitline;

a plurality of sub bitlines;

a main bitline load controller for controlling impedance between the main bitline and a power voltage source according to a first control signal, wherein the main bitline load controller is in an active state during a sensing operation of the main bit line;

a main bitline pull-up controller for providing a voltage to the main bitline according to a second control signal, wherein the main bitline pull-up controller is in an active state during a precharge operation; and

a current controller for controlling a current flowing from the main bitline to a ground according to a sensing voltage of one sub bitline of the plurality of the sub bitlines to induce a sensing voltage of the main bitline according to the current.