Method for fabricating metal-insulator-metal capacitor of semiconductor device with reduced patterning steps

1. A method for fabricating a metal-insulator-metal (MIM) capacitor of a semiconductor device, comprising steps of:

(a) forming a structure in which a lower metal film pattern and a dielectric film pattern are sequentially deposited on a first insulating film on a semiconductor substrate;

(b) simultaneously patterning the lower metal film pattern and the dielectric film pattern to form a first structure in a MIM capacitor region, in which a lower metal electrode film pattern and the dielectric film pattern are sequentially deposited on the first insulating film, and a second structure in a metal line region, in which a lower metal line film pattern and the dielectric film pattern are sequentially deposited on the first insulating film, wherein the lower metal electrode film pattern and the lower metal line film pattern are in direct contact with and formed on top of the first insulating film;

(c) removing the dielectric film pattern in the metal line region using a wet etching process to expose the lower metal line film pattern;

(d) forming a second insulating film to cover the dielectric film pattern in the MIM capacitor region and the lower metal line film pattern in the metal line region;

(e) simultaneously forming a trench that exposes the dielectric film pattern in the MIM capacitor region and a via hole that exposes the lower metal line film pattern in the metal line region by passing through the second insulating film; and

(f) forming an upper metal electrode film pattern and a via contact to respectively bury the trench and the via hole.

2. The method of claim 1 , wherein step (b) comprises:

forming a mask film pattern on the dielectric film pattern to expose the dielectric film pattern between the MIM capacitor region and the metal line region; and

sequentially removing the dielectric film pattern exposed by the mask film pattern and the lower metal film pattern through an etching process using the mask film pattern as an etching mask.

3. The method of claim 2 , wherein step (c) comprises:

removing the dielectric film pattern in the metal line region by performing an etching process in the dielectric film pattern; and

lifting off the mask film pattern on the removed dielectric film pattern.

4. The method of claim 3 , further comprising the step of removing the mask film pattern remaining in the MIM capacitor region.

5. The method of claim 3 , wherein the etching process is a wet etching process.

6. The method of claim 1 , wherein step (e) comprises:

forming a mask film pattern on the second insulating film, the mask film pattern having openings that expose surfaces of the second insulating film, in which the trench and the via hole are to be formed;

simultaneously forming the trench that exposes the dielectric film pattern in the MIM capacitor region and the via hole that exposes the lower metal line film pattern in the metal line region by performing the etching process in the exposed surfaces of the second insulating film using the mask film pattern as an etching mask; and

removing the mask film pattern.

7. The method of claim 1 , wherein the lower metal film pattern is formed of one of a Ti/TiN/Al/TiN film, a Ti/TiN/Al/Ti/TiN film, a Ti/Al/TiN film, and a Ti/Al/Ti/TiN film.

8. The method of claim 7 , wherein the uppermost TiN film has a thickness of 100 Å to 1000 Å.

9. The method of claim 1 , wherein the dielectric film pattern is formed of one of Si 2 O 3 , Si 3 N 4 and Ta 2 O 3 at a thickness of not more than 1000 Å.