Semiconductor apparatus and clock generation unit
View Patent ↗A semiconductor apparatus generates a clock signal used for scan test on an internal circuit of the semiconductor apparatus. The semiconductor apparatus includes a scan chain for performing input and output of data in the internal circuit, a clock generator for generating a launch clock signal for sending data to the internal circuit and a capture clock signal for capturing data from the internal circuit. The launch clock signal and the capture clock signal are generated based on a plurality of clock signals having different phases, and a pulse width of the plurality of clock signals is smaller than half of a cycle of the plurality of clock signals.
1. A semiconductor apparatus for generating a scan clock signal on an internal circuit of the semiconductor apparatus, comprising:
a scan chain performing input and output of data in the internal circuit;
a clock generator generating a launch clock signal for sending data to the internal circuit and a capture clock signal for capturing data from the internal circuit,
wherein the launch clock signal and the capture clock signal are generated based on a plurality of clock signals, received by the clock generator, having different phases, and
wherein a pulse width of the plurality of clock signals, received by the clock generator, is smaller than half of a cycle of the plurality of clock signals.
2. The semiconductor apparatus according to claim 1 , wherein the launch clock signal and the capture clock signal are obtained by a logic operation on the plurality of clock signals and a scan enable signal for switching between shift mode and capture mode of the scan chain.
3. The semiconductor apparatus according to claim 1 , wherein the launch clock signal and the capture clock signal are obtained by a logic operation on the plurality of clock signals and a scan enable signal for switching between shift mode and capture mode of the scan chain, and the logic operation includes exclusive-OR operation.
4. The semiconductor apparatus according to claim 1 , wherein the clock generator comprises at least one inverter and an exclusive-OR circuit.
5. The semiconductor apparatus according to claim 4 , wherein only one of the plurality of clock signals is directly connected to the exclusive-OR circuit.
6. The semiconductor apparatus according to claim 4 , wherein only one of the plurality of clock signals is directly connected to the inverter.
7. The semiconductor apparatus according to claim 1 , wherein the clock generator includes an OR circuit, an exclusive-OR circuit, and an inverter.
8. The semiconductor apparatus according to claim 7 , wherein the inverter inverts only one of the input test clock signal and outputs the inverted clock signal to the OR circuit.
9. The semiconductor apparatus according to claim 7 , wherein the first input terminal of the OR circuit is connected to the output terminal of the inverter, and the second input terminal of the OR circuit receives a scan enable signal.
10. The semiconductor apparatus according to claim 7 , wherein the output terminal of the OR circuit is connected to the input terminal of the exclusive-OR circuit.
11. The semiconductor apparatus according to claim 7 , wherein the first input terminal of the exclusive-OR circuit receives one of the plurality clock signals and the second input terminal of the exclusive-OR circuit is connected to the output terminal of the OR circuit.
12. The semiconductor apparatus according to claim 1 , wherein the clock generator includes a selector, an exclusive-OR circuit, a first inverter, and a second inverter.
13. The semiconductor apparatus according to claim 12 , wherein the input terminal of the first inverter receives one of the plurality of clock signals and the output terminal of the first inverter is connected to the input terminal of the exclusive-OR circuit.
14. The semiconductor apparatus according to claim 12 , wherein the input terminal of the second inverter receives one of the plurality of clock signals and the output terminal of the second inverter is connected to the input terminal of the selector.
15. The semiconductor apparatus according to claim 12 , wherein the first input terminal of the exclusive-OR circuit receives one of the plurality of clock signals and the second input terminal of the exclusive-OR circuit is connected to the output terminal of the first inverter.
16. The semiconductor apparatus according to claim 1 , wherein the clock generator sets the pulse width of the plurality of clock signals to approximately ¼ of the plurality of clock cycle of the clock signals.
17. The semiconductor apparatus according to claim 1 , wherein the semiconductor apparatus generates the scan clock signal at a frequency more than the frequency of a test clock signal supplied to the clock generator from a tester unit.
18. The semiconductor apparatus according to claim 1 , wherein the scan clock signal is generated at a frequency more than two times the frequency of a test clock signal supplied to the clock generator from a tester unit.
19. A digital circuit comprising:
a scan chain performing input and output of data in an internal circuit;
a clock generator generating a launch clock signal for sending data to the internal circuit and a capture clock signal for capturing data from the internal circuit,
wherein the launch clock signal and the capture clock signal are generated based on a plurality of clock signals, received by the clock generator, having different phases, and
wherein the digital circuit generates a scan clock signal at a frequency more than two times the frequency of a test clock signal supplied to the high speed clock generator from a tester unit.
20. A digital circuit comprising:
a scan chain performing input and output of data in an internal circuit;
a clock generator generating a launch clock signal for sending data to the internal circuit and a capture clock signal for capturing data from the internal circuit,
wherein the launch clock signal and the capture clock signal are generated based on a plurality of clock signals, received by the clock generator, having different phases,
wherein a pulse width of the plurality of clock signals is smaller than half of a cycle of the plurality of clock signals, received by the clock generator, and
wherein the clock generator comprises at least one inverter and an exclusive-OR circuit.