Method of forming semiconductor device having nanotube structures
View Patent ↗A semiconductor device having upright dielectric nanotubes at an inter-layer dielectric level and method of manufacturing such a device is disclosed. The use of a catalyst is proposed in the disclosed manufacturing flow that facilitates growth of upright dielectric nanotubes having ultra low-k values that form all or part of the dielectric material for an ILD. In one embodiment, carbon nanotubes form interlayer conducting vias. In another embodiment dielectric material nanotubes form reinforcing pillars. The integration of catalysts is proposed to accommodate both upright dielectric and upright conducting nanotube fabrication in the same layer.
1. A method comprising:
forming a conducting via at a first level of a workpiece, wherein the workpiece is an electronic semiconductor device workpiece;
forming a first layer comprising a plurality of dielectric nanotubes at the first level using a composite catalyst, wherein the composite catalyst comprises a material having a plurality of composite portions including a catalyst and a dielectric material, and at least a majority of the dielectric nanotubes are upright dielectric nanotubes;
forming at the first level a first dielectric layer of a first dielectric material, wherein the first dielectric layer is formed prior to formation of the plurality of dielectric nanotubes; and
forming at the first level a second dielectric layer of a second dielectric material, wherein the second dielectric layer is formed prior to formation of the plurality of dielectric nanotubes, and the second dielectric layer is at least partially removed prior to forming the plurality of dielectric nanotubes, and the first dielectric layer remains after at least partially removing the second dielectric layer.
2. The method of claim 1 , wherein the upright dielectric nanotubes comprise boron.
3. The method of claim 1 , wherein forming the first layer comprises forming the dielectric nanotubes using a tip-seed composite catalyst.
4. The method of claim 1 , wherein forming the first layer comprises forming the dielectric nanotubes using a root-seed composite catalyst.
5. The method of claim 1 , wherein forming the conductive via comprises forming the conducting via using an upright carbon nanotube.
6. The method of claim 5 , wherein forming the first layer comprises forming the dielectric nanotubes using a tip-seed composite catalyst.
7. The method of claim 5 , wherein forming the first layer comprises forming the dielectric nanotubes using a root-seed composite catalyst.
8. The method of claim 1 , wherein the upright dielectric nanotubes form a substantial portion of an inter-level dielectric layer of the electronic semiconductor device, wherein the substantial portion of the inter-level dielectric layer comprises the plurality of dielectric nanotubes forming greater than approximately 10% of the inter-level dielectric layer from a plan view.
9. The method of claim 8 , wherein the substantial portion of the inter-level dielectric layer comprises the plurality of dielectric nanotubes forming substantially all of the inter-level dielectric layer from a plan view.
10. The method of claim 1 wherein forming the conductive via comprises forming the conducting via using at least one of copper and aluminum.
11. The method of claim 1 , wherein forming the first layer comprises forming a layer comprising composite catalyst and forming the plurality of dielectric nanotubes at the layer comprising the composite catalyst.