IP Library Granted Patent US 8,446,343
Granted Patent B2
US 8,446,343 · App. 11/298,470 · Granted May 21, 2013

Image display apparatus

Inventors: Hajime Akimoto (Kokubunji, JP); Hiroshi Kageyama (Hachioji, JP)
Assignees: Hitachi Displays, Ltd.; Panasonic Liquid Crystal Display Co., Ltd.
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Quick Facts
Patent No.
US 8,446,343
App. No.
11/298,470
Granted
May 21, 2013
Kind
B2
Abstract

An image display apparatus capable of effecting displays high in both reliability and luminance. With the image display apparatus, a transistor switch is provided between a light emitting device and a drive transistor, and a voltage value expressed by formula (a gate voltage at an on-time of the transistor switch)—(the threshold voltage Vth of the drive transistor) is rendered smaller than a value of a voltage applied to a common electrode of the light emitting device.

Claims (17)

1. An image display apparatus comprising:

a gradation signal voltage generation circuit; and

a display region in which a plurality of pixels are arranged in a matrix fashion, and

wherein each pixel includes a light emitting device with luminance being controlled in analogue by the gradation signal voltage generation circuit, and a luminance control circuit for the light emitting device, the light emitting device of each pixel having first and second terminals,

wherein the luminance control circuit of each pixel comprises an nMOS transistor as a drive TFT having a source that is applied a constant voltage and operating in a saturation region,

wherein each pixel further comprises an nMOS transistor switch as a power supply switch and a reset switch,

wherein, for each pixel, the power supply switch is provided between the first terminal of the light emitting device and a drain of the drive TFT included in the luminance control circuit, the power supply switch has a drain side thereof connected to the first terminal of the light emitting device and a source side thereof connected to the drain of the drive TFT included in the luminance control circuit, and a gate voltage of the power supply switch is controlled by a power supply control line on a binary basis of ON/OFF,

wherein, for each pixel, the reset switch has a source thereof connected to the drain of the drive TFT, a drain thereof connected to a signal line via a signal storage capacitor and connected to a gate of the drive TFT, and a gate thereof connected to a reset control line,

wherein, for a pixel that is selected for writing:

in a signal voltage write time period that is a first half of one frame period, the power supply switch is first turned ON by a drive voltage applied by the power supply control line, the reset switch is subsequently turned ON by an RST signal applied via the reset control line so that current flows from a common electrode to the light emitting device via the drive TFT and the power supply switch, the power supply switch is turned OFF by the drive voltage applied by the power supply control line so that the drive TFT is turned OFF at a time when a voltage at the drain of the drive TFT becomes a threshold voltage Vth, a predetermined data signal voltage has already been applied to the signal line, and a difference between the data signal voltage and the threshold voltage Vth is input to the signal storage capacitor, and the reset switch is subsequently turned OFF by the RST signal of the reset control line so that the signal voltage is stored in the signal storage capacitor, thereby completing writing of the signal voltage to the pixel,

in a luminescence display time period that is subsequent second half of the one frame period, a predetermined triangular wave signal of an analog signal is input to each of the plurality of pixels via the signal line, the power supply switch is turned ON by the drive voltage applied by the power supply control line, and the threshold voltage Vth is input to the gate of the drive TFT if the triangular wave signal applied to the signal line is equivalent to the signal voltage written to the pixel in the signal voltage write time period so that a luminescence period of the light emitting device is determined according the signal voltage written to the pixel, and

wherein an on-voltage of the power supply switch that results from the drive voltage applied by the power supply control line represents a half-ON condition of the power supply switch rather than a complete-ON condition.

2. An image display apparatus according to claim 1 , wherein the light emitting device is an organic EL device.

3. An image display apparatus according to claim 1 , wherein the display region is formed on an insulating substrate.

4. An image display apparatus according to claim 1 , wherein a value of a voltage applied to the second terminal of the light emitting device varies depending on respective display colors of the light emitting device.

5. An image display apparatus according to claim 1 , wherein the luminance control circuit of the light emitting device controls analogue luminance of the respective pixels by modulating respective luminescence intensity of the light emitting device in one frame period.

6. An image display apparatus according to claim 1 , wherein the power supply switch of each pixel is controlled such that an operating point thereof at on-time occurs in a saturation region.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2018
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.; JAPAN DISPLAY INC.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 046988/0801 →
MERGER Recorded Dec 13, 2011
From: IPS ALPHA SUPPORT CO., LTD.
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 027482/0140 →
ATTACHED ARE (1) THE COMPANY SPLIT DOCUMENTS IN JAPANESE WITH ENGLISH TRANSLATION THEREOF AND (2) THE CERTIFICATE OF COMPANY SPLIT DOCUMENT IN JAPANESE WITH ENGLISH TRANSLATION, WHICH TOGETHER CONVEY 50% OWNERSHIP OF THE REGISTERED PATENTS AS LISTED IN THE ATTACHED TO EACH OF THE RECEIVING PARTIES (SEE PAGE 10, EXHIBIT 2-1, SECTION 1 OF THE ENGLISH TRANSLATION OF THE COMPANY SPLIT PLAN.) Recorded Dec 13, 2011
From: HITACHI, DISPLAYS, LTD.
To: HITACHI DISPLAYS, LTD.; IPS ALPHA SUPPORT CO., LTD.
Reel/Frame 027615/0589 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2005
From: AKIMOTO, HAJIME; KAGEYAMA, HIROSHI
To: HITACHI DISPLAYS, LTD.
Reel/Frame 017354/0646 →
Priority Claims (1)
JP 2005-008616 · Jan 17, 2005 · national
Continuity (1)
Related Publication 20060158398A1 · Jul 20, 2006