MOS transistor and manufacturing method thereof
View Patent ↗A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer and the insulation layer. The transistor includes a deep extended source/drain region, a first source/drain region that is deeper than the extended source/drain region, and a second source/drain region that is shallower than the extended source/drain region.
1. A manufacturing method of a MOS transistor, comprising:
forming a gate stack with a gate insulation layer and a gate electrode layer on a semiconductor substrate;
forming an oxide layer at the sidewall of the gate electrode layer;
forming a capping oxide layer on the oxide layer, wherein the capping oxide layer is formed as a middle temperature oxide (MTO) that is formed at a temperature of 700-780° C.;
forming an extended source/drain region having a predetermined depth by a first ion implantation process using the gate stack as an ion implantation mask;
forming a gate spacer layer on a sidewall of the gate stack; forming a first source/drain region that is deeper than the extended source/drain region by a second ion implantation process using the gate spacer layer as an ion implantation mask; and
forming a second source/drain region that is shallower than the extended source/drain region by a third ion implantation process using the gate spacer layer as an ion implantation mask.
2. The manufacturing method of claim 1 , wherein an impurity concentration of the third ion implantation process is higher than an impurity concentration of the first ion implantation process.
3. The manufacturing method of claim 2 , wherein the impurity concentration of the third ion implantation process is higher than an impurity concentration of the second ion implantation process.
4. The manufacturing method of claim 1 , wherein the predetermined depth of the extended source/drain region is 0.12-0.40 μm.
5. The manufacturing method of claim 4 , wherein the depth of the first source/drain region is 0.20-0.50 μm, and the depth of the second source/drain region is 0.10-0.35 μm.