System and method for aligning a quadrature encoder and establishing a decoder processing speed
View Patent ↗A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of encoder performance, and to assess the safety factor of a particular decoder processing speed. The system and method may also be used to indicate proper adjustment direction by displaying real-time error measurements during encoder alignment. The system measures a logic state width error and calculates alignment parameters, processing speed and a safety factor. The method allows a measured logic state width error to be used to calculate a minimum required processing speed and safety factor.
1. A method for determining a minimum required processing speed for a logic decoder comprising:
measuring two or more logic state widths; and
calculating said minimum required processing speed using said widths in combination with a desired number of processing cycles for deciding a logic state.
2. The method of claim 1 wherein said measuring comprises:
capturing rising and falling edges of one or more logic signals; and
determining a duration between said rising and falling edges.
3. The method of claim 2 further comprising:
using index pulses to generate interrupts in a controller, wherein said interrupts start and stop time-keeping intervals.
4. The method of claim 1 wherein said using said widths comprises:
determining an inequality between one of said widths and at least one other of said widths.
5. The method of claim 4 wherein said inequality is used to calculate a logic state width error.
6. The method of claim 1 wherein said logic decoder is a quadrature decoder.
7. A method for determining a safety factor of a logic decoder, said decoder having a processing speed, said method comprising:
measuring two or more logic state widths;
calculating a logic state width error;
choosing a number of processing cycles required to decide a logic state; and
calculating said safety factor using said logic state width error, said decoder processing speed and said chosen number of processing cycles.
8. The method of claim 7 wherein said measuring comprises:
capturing rising and falling edges of one or more logic signals; and
determining a duration between said rising and falling edges.
9. The method of claim 8 further comprising:
using index pulses to generate interrupts in a controller, wherein said interrupts start and stop time-keeping intervals.
10. The method of claim 7 wherein said calculating a logic state width error comprises:
determining an inequality between one of said widths and at least one other of said widths.
11. The method of claim 7 wherein said logic decoder is a quadrature decoder.
12. A system for analyzing logic encoder performance comprising:
a sampler, for capturing rising and falling edges of logic signals on channels of said encoder;
logic for determining two or more logic state widths using the said rising and falling edges and determining inequalities between one of said widths and at least one other of said widths;
logic to calculate logic state width error using said inequalities, and
logic to calculate a required decoder processing speed using said logic state width error in combination with a desired number of processing cycles for deciding a logic state.
13. A system for analyzing logic encoder performance comprising:
a sampler, for capturing rising and falling edges of logic signals on channels of said encoder;
logic for determining two or more logic state widths using the said rising and falling edges and determining inequalities between one of said widths and at least one other of said widths;
logic to calculate logic state width error using said inequalities, and
logic to calculate a decoder safety factor using said logic state width error in combination with a processing speed of said decoder.
14. The system of claim 12 or 13 , further comprising:
a controller for controlling said sampler; wherein said controlling comprises starting and stopping sampling intervals.
15. The system of claim 12 or 13 , further comprising:
logic to calculate logic state width error using said inequalities.
16. The system of claim 12 or 13 , further comprising:
a user interface.
17. The system of claim 16 wherein said user interface comprises:
a display, wherein said display shows said logic state width error.
18. The system of claim 12 or 13 , further comprising:
a resolution counter, said counter counting a number of codes per revolution.
19. The system of claim 12 or 13 , wherein said sampler detects index pulses of said logic encoder.