Readout circuit and nonvolatile semiconductor memory device

1. A readout circuit comprising:

a sense amplifier circuit configured to sense a data stored in a memory cell transistor based on a current flowing through said memory cell transistor and a reference current flowing through a dummy cell transistor; and

a voltage control circuit configured to apply a first voltage to a gate of said dummy cell transistor in a read operation,

wherein said memory cell transistor has a control gate and a floating gate, and

said voltage control circuit sets said first voltage such that a voltage between said gate and a source of said dummy cell transistor is lower than a second voltage between said control gate and a source of said memory cell transistor,

wherein a capacitance between said control gate and said floating gate is C 1 ,

a capacitance between said floating gate and a substrate surface is C 2 , and

said voltage control circuit sets said first voltage to be (C 1 /(C 1 +C 2 )) times said second voltage.

2. The readout circuit according to claim 1 ,

wherein said voltage control circuit sets said first voltage such that said dummy cell transistor operates in a transition region between a strong inversion region and a weak inversion region.

3. The readout circuit according to claim 1 ,

wherein said voltage control circuit sets said first voltage to a threshold voltage of said dummy cell transistor.

4. The readout circuit according to claim 1 ,

wherein said voltage control circuit includes:

a first resistance connected between an intermediate node and a terminal to which said second voltage is applied; and

a second resistance connected between said intermediate node and a ground terminal,

wherein said voltage control circuit sets a voltage of said intermediate node as said first voltage.

5. The readout circuit according to claim 4 ,

wherein values of said first resistance and said second resistance are designed such that said dummy cell transistor operates in a transition region between a strong inversion region and a weak inversion region.

6. The readout circuit according to claim 4 ,

wherein values of said first resistance and said second resistance are designed such that said first voltage is set to a threshold voltage of said dummy cell transistor.

7. The readout circuit according to claim 1 ,

wherein said dummy cell transistor has a control gate and a floating gate which are shorted with each other, and

said voltage control circuit applies said first voltage to said control gate of said dummy cell transistor.

8. The readout circuit according to claim 1 ,

wherein said dummy cell transistor is a single-gate type enhanced transistor, and

said voltage control circuit applies said first voltage to a gate of said enhanced transistor.

9. A readout circuit comprising:

a sense amplifier circuit configured to sense a data stored in a memory cell transistor based on a current flowing through said memory cell transistor and a reference current flowing through a dummy cell transistor; and

a voltage control circuit configured to apply a first voltage to a gate of said dummy cell transistor in a read operation,

wherein said memory cell transistor has a control gate and a floating gate, and

said voltage control circuit sets said first voltage such that a voltage between said gate and a source of said dummy cell transistor is lower than a second voltage between said control gate and a source of said memory cell transistor,

wherein said voltage control circuit includes:

a first resistance connected between an intermediate node and a terminal to which said second voltage is applied; and

a second resistance connected between said intermediate node and a ground terminal,

wherein said voltage control circuit sets a voltage of said intermediate node as said first voltage, and

wherein a capacitance between said control gate and said floating gate is C 1 ,

a capacitance between said floating gate and a substrate surface is C 2 ,

a value of said first resistance is R 1 ,

a value of said second resistance is R 2 , and

said R 1 and said R 2 are designed such that the following equation is satisfied:

C 1/( C 1 +C 2)= R 2/( R 1 +R 2).

10. A readout circuit comprising:

a sense amplifier circuit configured to sense a data stored in a memory cell transistor based on a current flowing through said memory cell transistor and a reference current flowing through a dummy cell transistor; and

a voltage control circuit configured to apply a first voltage to a gate of said dummy cell transistor in a read operation,

wherein said memory cell transistor has a control gate and a floating gate, and

said voltage control circuit sets said first voltage such that a voltage between said gate and a source of said dummy cell transistor is lower than a second voltage between said control gate and a source of said memory cell transistor,

wherein said source of said dummy cell transistor is connected to ground through a third resistance, and

said voltage control circuit sets said first voltage to said second voltage.

11. The readout circuit according to claim 10 ,

wherein a value of said third resistance is designed such that said dummy cell transistor operates in a transition region between a strong inversion region and a weak inversion region.

12. The readout circuit according to claim. 10 ,

wherein a value of said third resistance is designed such that a voltage between said gate and said source of said dummy cell transistor is set to a threshold voltage of said dummy cell transistor.

13. The readout circuit according to claim 10 ,

wherein a capacitance between said control gate and said floating gate is C 1 ,

a capacitance between said floating gate and a substrate surface is C 2 ,

said second voltage is VR,

said reference current is Iref, and

a value R 3 of said third resistance is given by the following equation:

R 3=( VR/I ref)( C 2/ C 1 +C 2).