Compact processor element for a scalable digital logic verification and emulation system
View Patent ↗A logic simulation acceleration processor optimized for multi-value logic level simulation of electronic systems described in hardware description languages.
1. A processor, for evaluating circuit signal values of an electronic design, comprising operand inputting electronic devices and circuitry for reading four or more operands, instruction input electronic devices and circuitry for reading one or more processor instructions, and encoding electronic devices and circuitry for encoding four or more circuit signal values onto a plurality of output bits, the processor further comprising electronic devices and circuitry for reading an input vector OLD, electronic devices and circuitry for reading a plurality of scalars SHIFT, XOUT, executing electronic devices and circuitry for executing a wide variable shift instruction comprising electronic devices and circuitry for replicating the scalar XOUT to the width of the processor output vector OUT; electronic devices and circuitry for shifting the input vector OLD to the right according to the binary value SHIFT; electronic devices and circuitry for bit-wise OR operation of the shifted OLD vector with the replicated XOUT vector, electronic devices and circuitry for assigning the result of the vector OR operation to the processor output vector OUT further comprising electronic devices and circuitry for reading an input vector NEW, electronic devices and circuitry for reading a plurality of input scalars ENABLE, WIDTH, and storing electronic devices and circuitry for storing a variable RSHAMT, executing electronic devices and circuitry for executing a replace range instruction by shifting the input vector NEW to the left according to the decimal value SHIFT on the condition that bit 0 of ENABLE is true; electronic devices and circuitry for shifting the input vector NEW to the right according to the decimal value RSHAMT assigned to be 32 minus SHIFT; electronic devices and circuitry for replacing some part of OLD with lower “WIDTH” plus 1 vector members of shifted vector NEW, electronic devices and circuitry for translating a decimal value of WIDTH to a binary mask, electronic devices and circuitry for assigning a replacement mask from a left shifted mask on the condition that the 0 bit of ENABLE is true, assigning from a right shifted mask if the 1 bit of ENABLE is true and the right shift amount RSHAMT is non zero, and assigning all bits to be zero if otherwise, electronic devices and circuitry for replacing some part of OLD with lower “WIDTH” plus 1 vector members of NEW shifted left if 0th bit of enable is true or shifted right by 32 minus shift if 0th bit of enable is false and bit-wise OR'ing the resulting combination of OLD and NEW with the result of replicated XOUT.
2. A method of programming an electronic device to perform evaluation processor operations wherein programming comprises one or more of the steps comprising the group: making fuses or anti-fuses conductive or non-conductive, injecting charge to floating gates, storing a binary pattern on a computer readable medium, applying current or voltage to a memory controlling a pass transistor, and recording a tape to define an image of conductive or non-conductive traces or polygons in a mask, the method comprising the steps of
configuring an electronic device to
read an input vector OLD,
read a plurality of scalars SHIFT, XOUT,
execute a wide variable shift instruction,
replicate the scalar XOUT to the width of the processor output vector OUT;
shift the input vector OLD to the right according to the binary shift value SHIFT;
bit-wise OR operation of the shifted OLD vector with the replicated XOUT vector,
assign the result of the vector OR operation to the processor output vector OUT, and
read a plurality of input scalars ENABLE, WIDTH, and store a variable RSHAMT,
execute a replace range instruction by shifting the input vector NEW to the left according to the decimal value SHIFT on the condition that bit 0 of ENABLE is true;
shift the input vector NEW to the right according to the decimal value RSHAMT assigned to be 32 minus SHIFT;
replace some part of OLD with lower “WIDTH” plus 1 vector members of shifted vector NEW,
translate a decimal value of WIDTH to a binary mask,
assign a replacement mask from a left shifted mask on the condition that the 0 bit of ENABLE is true and the right shift amount RSHAMT is non-zero, and assigning all bits to be zero if otherwise,
replace some part of OLD with lower “WIDTH” plus 1 vector members of NEW shifted left if 0 th bit of enable is true or shifted right by 32 minus SHIFT if 0 th bit of ENABLE is false and bit-wise OR the resulting combination of OLD and NEW with the result of replicated XOUT
and to read at least one instruction selected from the group of instructions following: AND, OR, NAND, NOR, XOR;
configuring an electronic device to read a plurality of operands which represent input circuit signal values selected from the group following: UNKNOWN, TRUE, FALSE, HIGH-IMPEDANCE;
configuring an electronic device to encode on a plurality of output bits the circuit signal values which result from applying said instruction to said plurality of operands,
wherein the plurality of operands simultaneously read and evaluated in one step are four or more, and wherein the plurality of circuit signal values read or encoded in one step are four or more.
3. An article of manufacture comprising a program product tangibly embodied on a computer readable medium to effect the programming of an electronic device to perform evaluation processor operations, the steps comprising:
configuring an electronic device to
read an input vector OLD,
read a plurality of scalars SHIFT, XOUT,
execute a wide variable shift instruction,
replicate the scalar XOUT to the width of the processor output vector OUT;
shift the input vector OLD to the right according to the binary shift value SHIFT;
bit-wise OR operation of the shifted OLD vector with the replicated XOUT vector,
assign the result of the vector OR operation to the processor output vector OUT, and
read a plurality of input scalars ENABLE, WIDTH, and store a variable RSHAMT,
execute a replace range instruction by shifting the input vector NEW to the left according to the decimal value SHIFT on the condition that bit 0 of ENABLE is true;
shift the input vector NEW to the right according to the decimal value RSHAMT assigned to be 32 minus SHIFT;
replace some part of OLD with lower “WIDTH” plus 1 vector members of shifted vector NEW,
translate a decimal value of WIDTH to a binary mask, assign a replacement mask from a left shifted mask on the condition that the 0 bit of ENABLE is true and the right shift amount RSHAMT is non-zero, and assigning all bits to be zero if otherwise,
replace some part of OLD with lower “WIDTH” plus 1 vector members of NEW shifted left if 0 th bit of enable is true or shifted right by 32 minus SHIFT if 0 th bit of ENABLE is false and bit-wise OR the resulting combination of OLD and NEW with the result of replicated XOUT
and to read one or more instructions selected from the group of instructions following: AND, OR, NAND, NOR, XOR;
configuring an electronic device to read a plurality of operands which represent input circuit signal values selected from the group following: UNKNOWN, TRUE, FALSE, HIGH-IMPEDANCE;
configuring an electronic device to encode on a plurality of output bits the circuit signal value which result from applying said instruction to said plurality of operands,
wherein the plurality of operands simultaneously read and evaluated in one step are four or more, and wherein the plurality of circuit signal values read or encoded in one step comprise four or more distinguishable values.