IP Library Assignment 030954/0787
Patent Assignment
Reel/Frame 030954/0787

Change of Name

Recorded: 2013-08-02 Pages: 5
Assignor
Assignee
SYNOPSYS EMULATION AND VERIFICATION
3, AVE JEANNE GARNERIN-BATIMENT B4, LE CORMORAN - AIR PARK PARIS SUD, ZAC DES HAUTS DE WISSOUS, WISSOUS, 91320, FRANCE
Covered Properties (13)
Functional Verification of Integrated Circuit Designs
Patent: 6,138,266 →
Application: 09/097,874 →
Functional Verification of Integrated Circuit Designs
Patent: 6,629,296 →
Application: 09/627,347 →
Tracing the Change of State of a Signal in a Functional Verification System
Patent: 6,629,297 →
Application: 09/738,259 →
Publication: US 2002/0116693
Functional Verification System
Patent: 6,691,287 →
Application: 09/738,260 →
Publication: US 2003/0041308
Tracing Different States Reached by a Signal in a Functional Verification System
Patent: 6,470,480 →
Application: 09/738,263 →
Publication: US 2002/0116689
Run-Time Controller in a Functional Verification System
Patent: 6,625,786 →
Application: 09/738,272 →
Publication: US 2002/0120907
Functional Verification of Both Cycle-Based and Non-Cycle Based Designs
Patent: 6,480,988 →
Application: 09/738,273 →
Publication: US 2002/0112217
A Compact Processor Element for a Scalable Digital Logic Verification and Emulation System
Patent: 7,509,602 →
Application: 11/307,130 →
Publication: US 2006/0277234
A Scalable System for Simulation and Emulation of Electronic Circuits Using Asymmetrical Evaluation and Canvassing Instruction Processors
Patent: 7,548,842 →
Application: 11/307,198 →
Publication: US 2006/0277019
A reconfigurable system for verification of electronic circuits using high-speed serial links to connect asymmetrical evaluation and canvassing instruction processors
Application: 11/307,206 →
Publication: US 2006/0277020
A system and method for simulation of electronic circuits generating clocks and delaying the execution of instructions in a plurality of processors
Application: 11/379,046 →
Publication: US 2006/0277428
A system and method for compiling a description of an electronic circuit to instructions adapted to execute on a plurality of processors
Application: 11/427,945 →
Publication: US 2007/0044079
Method for Delay Immune and Accelerated Evaluation of Digital Circuits by Compiling Asynchronous Completion Handshaking Means
Patent: 8,359,186 →
Application: 11/766,017 →
Publication: US 2007/0294075
Related Assignments (6)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Aug 9, 2001
From: GANESAN, SUBBU; BROUKHIS, LEONID ALEXANDER; NARAYANASWAMY, RAMESH; NIXON, IAN MICHAEL
To: THARAS SYSTEMS, INC.
Reel/Frame 012068/0421 →
Security Agreement Aug 18, 2003
From: THARAS SYSTEMS, INC.
To: SILICON VALLEY BANK
Reel/Frame 014384/0668 →
Release of Security Interest Jan 16, 2007
From: SILICON VALLEY BANK
To: THARAS SYSTEMS, INC.
Reel/Frame 018797/0190 →
Assignment of Assignor's Interest Feb 18, 2008
From: THARAS SYSTEMS INC.
To: EVE-USA, INC.
Reel/Frame 020518/0576 →
Assignment of Assignor's Interest May 13, 2008
From: EVE-USA, INC.
To: EVE-SA
Reel/Frame 020930/0678 →
Re-Record to Correct the Address of the Assignee, Previously Recorded on Reel 020930 Frame 0678. Jul 3, 2008
From: EVE-USA, INC
To: EVE-SA
Reel/Frame 021194/0423 →