A system and method for simulation of electronic circuits generating clocks and delaying the execution of instructions in a plurality of processors

1 . A system comprising a plurality of processors, a plurality of storage devices, interconnecting circuitry and a process for delaying the execution of at least one instruction,

the processors comprising

a time_step processor,

at least one instruction processor, and

at least one trigger processor;

the storage devices comprising

a time_step register,

at least one instruction register,

at least one time_delay register, and

at least one time_to_go register,

the interconnect circuitry comprising

at least one circuit for transferring each time_step from the time_step processor to at least one trigger processor, and

at least one circuit for transferring the time_delay to the trigger processor;

the process for delaying the execution of at least one instruction comprising the following steps:

executing at least one instruction when a time_to_go register first equals zero,

subtracting a time_step from at least one time_to_go register,

setting a time_step equal to the minimum value of time_to_go of at least one time_to_go register, and

setting time_to_go equal to time_delay at the start of the process.

2 . The system of claim 1 further comprising a current_time processor, a current_time register, a circuit for transferring each time_step from the time_step processor to the current time processor, and the process of accumulating time_steps from the start of the process to compute the current_time.

3 . A program product tangibly embodied in a computer-readable medium adapted to control the operation of at least one processor to perform the following process:

setting at least one time_to_go register to a certain non-zero time_delay value to start the process,

setting a time_step register to a time_step equal to the minimum non-zero value of time_to_go,

subtracting the time_step from at least one time_to_go register, and

executing at least one instruction when time_to_go first becomes zero.

4 . The program product of claim 3 further comprising the step of adding each time_step from the start of the process to determine the current_time.

5 . A method for generating at least one general purpose parameterized clock comprising the steps of:

reading one or more of the following: a begin_state_value, a begin_duration, a first_state_value, a first_state_duration, a second_state_value, a second_state_duration, and an optional clock_activity_duration,

initializing a begin time process by loading the time_delay with the begin_duration, and the instruction with setting the clock to the first_state_value and disabling the begin time process,

initializing a first time process by loading the time_delay with the first_state_duration, and

the instruction with setting the clock to the second_state_value,

initializing a second time process by loading the time_delay with the second_state_duration, and the instruction with setting the clock to the first_state_value,

setting the clock to the begin_state_value, and

loading the time_to_go with the begin_duration.

6 . The method of claim 5 further comprising at least one of the following: a global instruction disable method and an individual clock disable method wherein an individual clock disable method comprises:

maintaining a do_trigger register initialized with “true”,

performing clock inversion conditioned on the value of the do_trigger register,

maintaining a time_to_disable register initialized with the activity duration of the clock the same way as the time_to_go registers while do-trigger is “true”, and

assigning “false” to do_trigger when time_to_disable reaches 0.

7 . A system for delaying the start of a square wave clock signal composed of an equal amount of time at value-A and at its inverse comprising two instruction registers, two time_delay registers, two time_to_go registers, and a time step register, and a method comprising the steps following:

delaying the start of clock by loading a first time_to_go-A register from its time_delay-A register with the amount of time to delay starting the clock,

setting the time_step to the minimum non-zero time_to_go,

subtracting the time_step from the time_to_go-A, and

executing instruction-A to set the value of the clock to value-A and start the clock state,

setting the time_to_go-B register from its time_delay-B register with one-half of a clock period,

setting the time_step to the minimum non-zero time_to_go,

subtracting the time_step from the time_to_go-B, and

executing instruction-B to invert the value of the clock and restart the clock state whereby two states are modeled.

8 . The system of claim 7 for delaying the start of a clock signal composed of an certain amount of time at value-B and a certain amount of time at value-C further comprising

three instruction registers, three time_delay registers, three time_to_go registers, and a time step register, and a method comprising the steps following:

delaying the start of clock by loading a first time_to_go-A register from its time_delay-A register with the amount of time to delay starting the clock, setting the time_step to the minimum non-zero time_to_go, subtracting the time_step from the time_to_go-A, and

executing instruction-A to set the value of the clock to value-B, and start the phase one clock state,

setting the time_to_go-B register from its time_delay-B register with the amount of time the clock is defined to be at value-B, setting the time_step to the minimum non-zero time_to_go, subtracting the time_step from the time_to_go-B, and executing instruction-B to set the value of the clock to value C and start the phase two clock state,

setting the time_to_go-C register from its time_delay-C register with the amount of time the clock is defined to be at value-C, setting the time_step to the minimum non-zero time_to_go, subtracting the time_step from the time_to_go-C, and executing instruction-C to set the value of the clock to value B and start the phase one clock state whereby three states are modeled.

9 . A method for advancing time comprising the steps of finding a minimum value of time_to_go and subtracting the minimum value from all time_to_go registers.

10 . The method of claim 9 further comprising compiling a Verilog delay instruction into a time_delay, a time_step instruction and trigger instruction.

11 . The method of claim 9 for executing a plurality of evaluation instructions to generate a periodic clock signal within the array of processors whereby the host control interface is not interrupted to insert clock signals, the method further comprising the steps following: maintaining the

current time T in ticks as a register vector, initialized to 0,

maintaining a set of time variables R

initializing the variables R to the initial duration of the corresponding clock,

computing the minimum (M) of the values of these variables

incrementing T by M,

decrementing R variables by M, wherein for those clocks corresponding to R variables that are equal to 0,

executing at least one of the following instructions:

updating the value of the clock signal either to the inverse of the current value, or to the first phase value if the current value is X AND assigning the phase duration corresponding to the new value of the clocks (pos or neg) to the corresponding R variables,

sending the updated value of T to the host simulator: for the $display($time, . . . ) calls and $dumpvars to work correctly, and

injecting a time advance mark to the signal trace stream.