IP Library Granted Patent US 7,485,517
Granted Patent B2
US 7,485,517 · App. 11/308,560 · Granted Feb 3, 2009

Fabricating method of semiconductor device

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Quick Facts
Patent No.
US 7,485,517
App. No.
11/308,560
Granted
Feb 3, 2009
Kind
B2
Abstract

A method for fabricating a semiconductor device is provided. First, a substrate is provided, and a first-type MOS (metallic oxide semiconductor) transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor are formed on the substrate. Then, a first stress layer is formed to overlay the substrate, the first-type MOS transistor, the I/O second-type MOS transistor, and the core second-type MOS transistor. Then, at least the first stress layer on the core second-type MOS transistor is removed to reserve at least the first stress layer on the first-type MOS transistor. Finally, a second stress layer is formed on the core second-type MOS transistor.

Claims (9)

1. A method for fabricating a semiconductor device, comprising:

providing a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon;

forming a first stress layer to overlay the substrate, the first-type MOS transistor, the I/O second-type MOS transistor, and the core second-type MOS transistor;

removing the first stress layer on the core second-type MOS transistor to reserve the first stress layer on the first-type MOS transistor and the I/O second-type MOS transistor; and

forming a second stress layer on the core second-type MOS transistor and the first stress layer on the I/O second-type MOS transistor and not on the first stress layer formed on the first-type MOS transistor, wherein one of the first and the second stress layers is a tensile stress layer and the other is a compressive stress layer.

2. The method for fabricating the semiconductor device of claim 1 , wherein if the first-type MOS transistor is an N-channel MOS (NMOS) transistor and the I/O second-type MOS transistor and the core second-type MOS transistor are P-channel MOS (PMOS) transistors, the first stress layer is the tensile stress layer and the second stress layer is the compressive stress layer.

3. The method for fabricating the semiconductor device of claim 1 , wherein if the first-type MOS transistor is a P-channel MOS (PMOS) transistor and the I/O second-type MOS transistor and the core second-type MOS transistor are N-channel MOS (NMOS) transistors, the first stress layer is the compressive stress layer and the second stress layer is the tensile stress layer.

4. The method for fabricating the semiconductor device of claim 1 , wherein the first stress layer is made of a material comprises silicon nitride.

5. The method for fabricating the semiconductor device of claim 1 , wherein the second stress layer is made of a material comprises silicon nitride.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2006
From: LEE, KUN-HSIEN; HUANG, CHENG-TUNG; HUNG, WEN-HAN; TING, SHYH-FANN; JENG, LI-SHIAN; CHENG, TZYY-MING; LIANG, CHIA-WEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 017432/0817 →