Semiconductor device and method of manufacturing the semiconductor device
View Patent ↗A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gate insulation layer is disposed on the silicon substrate in the gate forming region. A second gate insulation layer is disposed on a sidewall of the first silicon epitaxial layer pattern. A second silicon epitaxial layer pattern is disposed in the gate forming region and on the first silicon epitaxial layer pattern. A pair of second source/drain regions is disposed on the second silicon epitaxial layer pattern. A third gate insulation layer exposes the second silicon epitaxial layer pattern in the gate forming region and covers the pair of second source/drain regions. A gate is disposed on the second silicon epitaxial layer pattern in the gate forming region.
1. A method of manufacturing a semiconductor device, comprising:
forming a pair of first source/drain regions on a silicon substrate;
forming an insulation layer pattern and a first silicon epitaxial layer pattern defining a gate forming region to expose the silicon substrate between the pair of first source/drain regions;
forming a first gate insulation layer on the silicon substrate in the gate forming region;
forming a second gate insulation layer on a sidewall of the first silicon epitaxial layer pattern;
forming a second silicon epitaxial layer pattern in the gate forming region and on the first silicon epitaxial layer pattern;
implanting impurities into a periphery of the second silicon epitaxial layer in the gate forming region to form a pair of second source/drain regions;
partially etching the second silicon epitaxial layer in the gate forming region to form a second silicon epitaxial layer pattern;
forming a third gate insulation layer that exposes a surface of the second silicon epitaxial layer pattern in the gate forming region and that covers lateral sides of the pair of second source/drain regions; and
forming a gate on an exposed surface of the second silicon epitaxial layer pattern.
2. The method according to claim 1 , wherein forming the pair of first source/drain regions comprises:
forming a buffer oxide layer on the silicon substrate;
forming a mask pattern on the buffer oxide layer such that the buffer oxide layer is partially exposed by the mask pattern;
implanting impurities into the silicon substrate through the use of the mask pattern as an ion implantation mask; and
removing the buffer oxide layer.
3. The method according to claim 1 , wherein the first gate insulation layer is formed by oxidation of a surface of the silicon substrate in the gate forming region, and the second gate insulation layer is formed by oxidation of sidewalls of the first silicon epitaxial layer pattern.
4. The method according to claim 1 , wherein the pair of second source/drain regions is formed above the pair of first source/drain regions.
5. The method according to claim 1 , wherein forming the insulation layer pattern and the first silicon epitaxial layer pattern comprises:
sequentially forming the first silicon epitaxial layer and the first insulation layer on the silicon substrate including the pair of first source/drain regions;
patterning the insulation layer and the first silicon epitaxial layer to expose the silicon substrate between the pair of first source/drain regions; and
removing the insulation layer pattern.
6. The method according to claim 1 wherein implanting impurities comprises implanting ions to form the pair of second source/drain regions.