Semiconductor device and method of manufacturing the same
View Patent ↗A semiconductor device having a vertical gate and method of manufacturing the same are disclosed. An example semiconductor device includes a pair of first source/drain regions formed apart from each other by a predetermined distance on a silicon substrate, a first silicon epitaxial layer formed on the pair of first source/drain regions, a vertical gate insulation layer formed at both sidewalls of the first silicon epitaxial layer, and a second silicon epitaxial layers formed on the first silicon epitaxial layer and on the gate insulation layer. The example device includes a pair of second source/drain regions formed in the second silicon epitaxial layer formed on the first silicon epitaxial layer, at positions above the pair of first source/drain regions, and a plurality of vertical gates respectively connected to the second silicon epitaxial layer formed on the gate insulation layer and to the pair of second source/drain regions.
1. A method of manufacturing a semiconductor device, comprising:
forming a pair of first source/drain regions apart from each other on a silicon substrate;
forming a buffer oxide layer having a vertical transistor forming region exposing the pair of first source/drain regions;
forming a first silicon epitaxial layer in the vertical transistor forming region;
etching the buffer oxide layer so as to form a vertical gate forming region at a position laterally exterior to the pair of first source/drain regions;
forming a vertical gate insulation layer in the vertical gate forming region;
forming a second silicon epitaxial layer respectively in the vertical gate forming region and on the first silicon epitaxial layer;
forming a pair of second source/drain regions, at positions above the pair of first source/drain regions, in the second silicon epitaxial layer formed on the first silicon epitaxial layer; and
forming a plurality of vertical gates respectively connected to the second silicon epitaxial layer formed on the gate insulation layer and to the pair of second source/drain regions.
2. The method of claim 1 , wherein the gate insulation layer is formed by oxidation of a sidewall of the first silicon epitaxial layer.
3. The method of claim 1 , wherein the second silicon epitaxial layer formed on the first silicon epitaxial layer is formed of polysilicon so as to be used as an electrode.
4. The method of claim 1 , wherein the gate insulation layer is also formed on the silicon substrate under the second silicon epitaxial layer under the gate, by oxidation of a surface of the silicon substrate.