NOR-type flash memory device and manufacturing method thereof
View Patent ↗A flash memory device that has a structure capable of preventing gate stack damage, and a method of manufacturing the same, is presented. The method includes forming a first photo resist pattern to open a common source region on a substrate where a shallow trench isolation region, a tunnel oxide layer, and a gate stack including a floating gate, a dielectric layer and a control gate are formed, removing an insulating layer in the shallow trench isolation region with using the first photo resist pattern as a mask, and removing the first photo resist pattern. The method further includes depositing a buffer oxide layer on surface of the substrate to cover the gate stack and the common source region, forming a second photo resist pattern on surface of the substrate including the buffer oxide layer to open the common source region, and injecting dopants to the common source region by using the second photo resist pattern as a mask.
1. A method of manufacturing a NOR-type flash memory device, comprising:
forming a first photoresist pattern to open a common source region on a substrate where a shallow trench isolation region, a tunnel oxide layer, and a gate stack that includes a floating gate, a dielectric layer and a control gate, are formed;
forming a trench in the common source region by removing an insulating layer in the shallow trench isolation region by using the first photo resist pattern as a mask;
removing the first photo resist pattern;
depositing a buffer oxide layer on a surface of the substrate to cover the gate stack and the trench;
forming a second photo resist pattern on surface of the substrate including the buffer oxide layer to open the buffer oxide layer formed on the trench; and
forming the common source region by injecting dopants into the trench which the buffer oxide layer covered using the second photo resist pattern as a mask.
2. The method of claim 1 , wherein the dielectric layer is oxide-nitride-oxide layer.
3. A NOR type flash memory device, comprising:
a Substrate having a shallow trench isolation region;
a tunnel oxide layer disposed on untrenched portions of the substrate;
a gate stack disposed on the tunnel oxide layer, the gate stack including a floating gate, a dielectric layer, and a control gate;
a buffer oxide layer having a thickness of less than 100 Å disposed on surfaces of the floating gate, dielectric layer, control gate and the trench isolation layer;
a common source region formed subsequent to said disposing of said buffer oxide layer, and
a common source line that electrically interconnects sources of each of a plurality of flash memory cells, wherein dopants are injected into the common source region
wherein the buffer oxide layer prevents the gate stack from being damaged from a self-aligned source (SAS) process and an ion implantation process which form the common source line.