Semiconductor device and method of manufacturing the semiconductor device
View Patent ↗A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide.
1. A method of manufacturing a semiconductor device, comprising:
forming a drain silicide on a semiconductor substrate;
forming a drain region at both sides of the drain silicide;
forming a gate nitride layer on the drain silicide;
forming a first epitaxial layer on lateral sides of the gate nitride layer;
forming a protection nitride layer on the first epitaxial layer and the gate nitride layer;
etching the protection nitride layer and the gate nitride layer to form a trench;
forming a first gate insulation layer on the drain silicide;
forming a gate oxide layer on a portion of the first epitaxial layer exposed by the trench;
forming a second epitaxial layer on the first epitaxial layer after removal of the protection nitride layer;
filling the trench with polysilicon to form a gate electrode;
ion-implanting impurities on the second epitaxial layer to form a source region;
forming a second gate insulation layer on the gate electrode and the gate oxide layer;
forming a source suicide on the second gate insulation layer;
forming an interlayer insulation layer on the second epitaxial layer, the source region and the source silicide;
forming a source contact hole to expose a portion of the source silicide;
forming a gate contact hole to expose a portion of the gate electrode; and
forming a drain contact hole to expose a portion of the drain silicide.
2. The method according to claim 1 , wherein forming the gate oxide layer comprises reacting the first epitaxial layer with oxygen gas.
3. The method according to claim 1 , wherein at least one of the source suicide and the drain suicide comprises cobalt, tantalum or nickel.
4. The method according to claim 1 , wherein ion-implanting impurities on the second epitaxial layer to form the source region comprises ion-implanting high-concentration impurities.
5. The method according to claim 1 , wherein forming the drain region comprises ion-implanting high-concentration impurities.
6. The method according to claim 5 , wherein ion-implanting impurities on the second epitaxial layer to form the source region comprises ion-implanting high-concentration impurities.
7. The method according to claim 1 , wherein the gate electrode, the source region and the drain region are formed in a vertical structure.
8. The method of claim 1 , wherein the second gate insulation layer and the source silicide fill in the second epitaxial layer.