Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor device according to a exemplary embodiment of the present invention includes a reverse spacer exposing a part of an epitaxial silicon layer on a silicon substrate, a gate oxide layer on at least the epitaxial silicon layer and a gate polysilicon layer on the gate oxide layer and at least part of the reverse spacer, and source/drain terminals including a first doped (shallow junction) region in the silicon substrate at a position exterior to the exposed epitaxial silicon layer and a second doped (deep junction) region neighboring the first doped region. The semiconductor device can thus have an epitaxial silicon channel of nanometer size, an ultra-shallow junction, and a deep junction.
1. A semiconductor device, comprising:
a reverse spacer exposing a part of an epitaxial silicon layer on a silicon substrate;
a gate oxide layer on the epitaxial silicon layer;
a gate polysilicon layer on the gate oxide layer and at least in part on the reverse spacer; and
source/drain terminals comprising a first doped region in the silicon substrate at a position exterior to the exposed epitaxial silicon layer and a second doped region neighboring the first doped region.
2. The semiconductor device of claim 1 , wherein the epitaxial silicon layer comprises strained silicon.
3. The semiconductor device of claim 1 , wherein the first doped region has a shallow junction.
4. The semiconductor device of claim 1 , wherein the second doped region has a deep junction.
5. The semiconductor device of claim 1 , further comprising a raised source/drain layer on the second doped region.
6. The semiconductor device of claim 5 , further comprising a metal suicide layer on the raised source/drain layer and on the gate polysilicon layer.
7. A semiconductor device, comprising:
a reverse spacer exposing a part of a highly doped epitaxial silicon layer on a silicon substrate;
an undoped epitaxial silicon layer under the highly doped epitaxial silicon layer;
a gate oxide layer on the highly doped epitaxial silicon layer;
a gate polysilicon layer on the gate oxide layer and at least in part on the reverse spacer; and
source/drain terminals comprising a first doped region in the silicon substrate at a position exterior to the exposed highly doped epitaxial silicon layer and a second doped region neighboring the first doped region.
8. The semiconductor device of claim 7 , wherein the epitaxial silicon layer comprises strained silicon.
9. The semiconductor device of claim 7 , wherein the first doped region has a shallow junction.
10. The semiconductor device of claim 7 , wherein the second doped region has a deep junction.
11. The semiconductor device of claim 7 , further comprising a raised source/drain layer on the second doped region.
12. The semiconductor device of claim 11 , further comprising a metal suicide layer on the raised source/drain layer and on the gate polysilicon layer.
13. A method of manufacturing a semiconductor device, comprising:
introducing germanium ions into a silicon substrate;
forming a first epitaxial silicon layer on the silicon substrate;
forming a hard mask pattern on the first epitaxial silicon layer;
forming a second epitaxial silicon layer on the first epitaxial silicon layer at a position exposed by the hard mask pattern;
removing the hard mask pattern;
forming a reverse spacer on a sidewall of the second epitaxial silicon layer so as to expose a part of the first epitaxial silicon layer;
forming a gate oxide layer on at least the exposed first epitaxial silicon layer;
forming a gate polysilicon layer on the gate oxide layer and at least in part on the reverse spacer;
forming a shallow junction region in the substrate, at least in part under the reverse spacer;
forming a gate spacer on sidewalls of the gate polysilicon layer; and
forming a deep junction region neighboring the shallow junction region so as to form source/drain terminals.
14. The method of claim 13 , further comprising introducing dopants into the second epitaxial silicon layer so as to form a raised source/drain.
15. The method of claim 14 , further comprising forming a metal silicide layer on the raised source/drain and on the gate polysilicon layer.
16. A method of manufacturing a semiconductor device, comprising:
sequentially forming an undoped first epitaxial silicon layer and a highly doped second epitaxial silicon layer on a silicon substrate;
forming a hard mask pattern on the second epitaxial silicon layer;
forming a third epitaxial silicon layer on the second epitaxial silicon layer at a position exterior exposed by the hard mask pattern;
removing the hard mask pattern;
forming a reverse spacer on a sidewall of the third epitaxial silicon layer so as to expose a part of the second epitaxial silicon layer;
forming a gate oxide layer on at least the exposed second epitaxial silicon layer;
forming a gate polysilicon layer on the gate oxide layer and at least in part on the reverse spacer;
forming a first doped region under the reverse spacer;
forming a gate spacer on sidewalls of the gate polysilicon layer; and
forming a second doped region neighboring the first doped region so as to form source/drain terminals.
17. The method of claim 16 , further comprising introducing dopants into the third epitaxial silicon layer so as to form a raised source/drain.
18. The method of claim 17 , further comprising forming a metal silicide layer on the raised source/drain and on the gate polysilicon layer.
19. The method of claim 16 , wherein the first doped region has a shallow junction.
20. The method of claim 16 , wherein the second doped region has a deep junction.