IP Library Granted Patent US 7,442,653
Granted Patent B2
US 7,442,653 · App. 11/316,634 · Granted Oct 28, 2008

Inter-metal dielectric of semiconductor device and manufacturing method thereof including plasma treating a plasma enhanced fluorosilicate glass

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Quick Facts
Patent No.
US 7,442,653
App. No.
11/316,634
Granted
Oct 28, 2008
Kind
B2
Abstract

An exemplary manufacturing method of an inter-metal dielectric of a semiconductor device according to an embodiment of the present invention includes forming a first silicon-rich oxide (SRO) layer on a silicon substrate provided with or otherwise having a copper line layer therein, forming a plasma enhanced fluorosilicate glass (PEFSG) layer on the first SRO layer, plasma-treating the PEFSG layer, and forming a second SRO layer on the plasma-treated PEFSG layer. According to the present invention, the thickness of the second SRO layer of the inter-metal dielectric can be reduced. Consequently, process cost can be reduced, and the total thickness of the inter-metal dielectric can be reduced so as to lower the dielectric constant thereof, reduce the aspect ratio of any via holes that are subsequently formed in the inter-metal dielectric, and potentially increase the yield as a result of the reduced via hole aspect ratio.

Claims (23)

1. A method of manufacturing a dielectric layer in a semiconductor device, comprising:

forming a first silicon-rich oxide (SRO) layer on a silicon substrate having a copper line layer therein;

forming a plasma enhanced fluorosilicate glass (PEFSG) layer on the first SRO layer;

forming a passivation layer which suppresses a fluorine-outgassing at an upper surface of the PEFSG layer by plasma-treating the PEFSG layer with a first plasma containing an oxygen source and subsequently with a second plasma containing a source of nitrogen and oxygen; and

forming a second silicon-rich oxide (SRO) layer on the plasma-treated PEFSG layer.

2. The manufacturing method of claim 1 , further comprising, before forming the first silicon rich oxide (SRO) layer, forming a silicon nitride layer.

3. The manufacturing method of claim 2 , wherein the silicon nitride layer provides an etch-stop function.

4. The manufacturing meted of claim 1 , wherein the first plasma comprises an oxygen (O 2 ) plasma.

5. The manufacturing method of claim 1 , wherein the second plasma comprises a nitrogen oxide plasma.

6. The manufacturing method of claim 1 , wherein plasma-treating the PEFSG layer comprises sequentially treating the PEFSG layer with an oxygen plasma and a nitrogen oxide plasma.

7. The manufacturing method of claim 1 , wherein the first SRO layer has a thickness of 300-500 Å, and the PEFSG layer has a thickness of 3000-6000 Å.

8. The manufacturing method of claim 1 , wherein the second SRO layer has a thickness of 1000-2000 Å.

9. The manufacturing method of claim 1 , wherein the first SRO layer has a thickness of 300-500 Å, the PEFSG layer has a thickness of 3000-6000 Å, and the second SRO layer has a thickness of 1000-2000 Å.

10. A dielectric layer in a semiconductor device, comprising;

a first silicon-rich oxide (SRO) layer on a silicon substrate having a copper layer therein;

a plasma enhanced fluorosilicate glass (PEFSG) layer on the first SRO layer;

a passivation layer on the surface of the PEFSG layer to suppress a fluorine-outgassing at an upper surface of the PEFSG layer, wherein the passivation layer is formed by sequentially treating the PEFSG layer with a first plasma containing an oxygen source and a second plasma containing a source of nitrogen and oxygen; and

a second SRO layer on the passivation layer.

11. The dielectric layer of claim 10 , wherein the passivation layer comprises a plasma-treated surface of the PEFSG layer.

12. The dielectric layer of claim 10 , further comprising a silicon nitride layer under the first SRO layer.

13. The dielectric layer of claim 10 , wherein the first SRO layer has a thickness of 300-500 Å, and the PEFSG layer has a thickness of 3000-6000 Å.

14. The dielectric of claim 10 , wherein the second SRO layer has a thickness of 1000-2000 Å.

15. The dielectric of claim 10 , wherein the first SRO layer has a thickness of 300-500 Å, the PEFSG layer has a thickness of 3000-6000 Å, and the second SRO layer has a thickness of 1000-2000 Å.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017749 FRAME 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.". Recorded Jun 21, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017821/0670 →
CHANGE OF NAME Recorded Jun 8, 2006
From: DONGANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017749/0335 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2005
From: LEE, TAE-YOUNG
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 017382/0186 →