Switched capacitor circuit type digital/analog converter capable of suppressing change of setting error

1. A digital/analog converter of a switched capacitor circuit type, comprising:

at least one capacitor;

at least one power supply terminal;

at least one output terminal;

a switch circuit adapted to carry out a charging operation upon said capacitor so that a charge is stored in said capacitor and then carry out a discharging operation upon said capacitor to selectively discharge said charge to one of said power supply terminal and said output terminal in accordance with a digital input data signal,

wherein said switch circuit is further adapted to make said capacitor have no charge after said discharging operation is carried out.

2. The digital/analog converter as set forth in claim 1 , wherein said switch circuit is further adapted to make said capacitor in a floating state with no charge after said discharging operation is carried out.

3. The digital/analog converter as set forth in claim 1 , wherein said switch circuit is further adapted to repeat said charging and discharging operations to convert said digital input data signal successively into analog signals.

4. The digital/analog converter as set forth in claim 1 , being incorporated into a multi-level digital/analog converter.

5. The digital/analog converter as set forth in claim 1 , being incorporated into a digital/analog converter section of a multi-bit ΔΣ analog/digital converter.

6. The digital/analog converter as set forth in claim 1 , being incorporated into a multi-level digital/analog converter section of a multi-bit digital/analog converter.

7. A digital/analog converter of a switched capacitor circuit type, comprising:

a first power supply terminal adapted to receive a first power supply voltage;

a second power supply terminal adapted to receive a second power supply voltage lower than said first power supply voltage;

a third power supply terminal adapted to receive a third power supply voltage lower than said second power supply voltage;

first and second output terminals;

a first capacitor having first and second terminals;

a second capacitor having third and fourth terminals;

a first switch circuit adapted to connect the first terminal of said first capacitor to said first power supply terminal in response to a first clock signal and to said second power supply terminal in response to a second clock signal;

a second switch circuit adapted to connect the third terminal of said second capacitor to said third power supply terminal in response to said first clock signal and to said second output terminal in response to said second clock signal;

a third switch circuit adapted to connect the second terminal of said first capacitor to said second power supply terminal in response to said first clock signal, to said first output terminal in response to said second clock signal when a digital input signal indicates a first value, to said second power supply terminal in response to said second clock signal when said digital input signal indicates a second value, and to said second power supply terminal in response to said second clock signal when said digital input signal indicates a third value; and

a fourth switch circuit adapted to connect the fourth terminal of said second capacitor to said second power supply terminal in response to said first clock signal, to said second output terminal in response to said second clock signal when said digital input signal indicates said first value, to said first output terminal in response to said second clock signal when said digital input signal indicates said second value, and to said second power supply terminal when said digital input signal indicates said third value.

8. The digital/analog converter as set forth in claim 7 , being incorporated into a multi-level digital/analog converter.

9. The digital/analog converter as set forth in claim 7 , being incorporated into a digital/analog converter section of a multi-bit ΔΣ analog/digital converter.

10. The digital/analog converter as set forth in claim 7 , being incorporated into a multi-level digital/analog converter section of a multi-bit digital/analog converter.

11. A digital/analog converter of a switched capacitor circuit type, comprising:

a first power supply terminal adapted to receive a first power supply voltage;

a second power supply terminal adapted to receive a second power supply voltage lower than said first power supply voltage;

a third power supply terminal adapted to receive a third power supply voltage lower than said second power supply voltage;

an output terminal;

a capacitor having first and second terminals;

a first switch circuit adapted to connect the first terminal of said capacitor to said first power supply terminal in response to a first clock signal when a digital input signal indicates a first value, to said third power supply terminal in response to said first clock signal when said digital input signal indicates a second value, and to said second power supply terminal in response to a second clock signal; and

a second switch circuit adapted to connect the second terminal of said capacitor to said second power supply terminal in response to said first clock signal, to said output terminal in response to said second clock signal when said digital input signal indicates a third value, and to said second power supply terminal in response to said second clock signal when said digital input signal indicates a fourth value.

12. The digital/analog converter as set forth in claim 11 , being incorporated into a multi-level digital/analog converter.

13. The digital/analog converter as set forth in claim 11 , being incorporated into a digital/analog converter section of a multi-bit ΔΣ analog/digital converter.

14. The digital/analog converter as set forth in claim 11 , being incorporated into a multi-level digital/analog converter section of a multi-bit digital/analog converter.

15. A digital/analog converter comprising:

a first power supply terminal adapted to receive a first power supply voltage;

a second power supply terminal adapted to receive a second power supply voltage lower than said first power supply voltage;

an output terminal;

a capacitor having first and second terminals;

a first switch circuit adapted to connect the first terminal of said capacitor to said first power supply terminal in response to a first clock signal, to said second power supply terminal in response to a second clock signal when a digital input signal indicates a first value, to said output terminal in response to said second clock signal when said digital input signal indicates a second value, and to said second power supply terminal in response to said second clock signal when said digital input signal indicates a third value; and

a second switch circuit adapted to connect the second terminal of said capacitor to said second power supply terminal in response to said first clock signal, to said output terminal in response to said second clock signal when said digital input signal indicates a first value, and to said second power supply terminal in response to said second clock signal when said digital input signal indicates said second value or a third value.

16. The digital/analog converter as set forth in claim 15 , being incorporated into a multi-level digital/analog converter.

17. The digital/analog converter as set forth in claim 15 , being incorporated into a digital/analog converter section of a multi-bit ΔΣ analog/digital converter.

18. The digital/analog converter as set forth in claim 15 , being incorporated into a multi-level digital/analog converter section of a multi-bit digital/analog converter.

19. A digital/analog converter of a switched capacitor circuit type, adapted to receive a digital signal and to output an analog signal corresponding to said digital signal, comprising:

a first power supply terminal adapted to receive a first power supply voltage;

a second power supply terminal adapted to receive a second power supply voltage different from said first power supply voltage;

a capacitor;

a first switch circuit adapted to connect one terminal of said capacitor to said first power supply terminal in response to a first clock signal and to said second power supply terminal in response to a second clock signal; and

a second switch circuit adapted to connect another terminal of said capacitor to said second power supply terminal in response to said first clock signal and to select one of said second power supply terminal and an output terminal in accordance with a value of said digital signal in response to said second clock signal.