Method for forming an intermetal dielectric layer using low-k dielectric material and a semiconductor device manufactured thereby

1. A method for forming an intermetal dielectric layer between metal wirings, comprising the steps of:

(a) forming a metal layer on a semiconductor substrate;

(b) forming a plurality of metal wiring patterns by etching the metal layer selectively;

(c) forming a first dielectric layer on the substrate and the plurality of metal wiring patterns;

(d) forming a SiOC layer on portions of the first dielectric layer above the metal wiring patterns and in a gap between sidewalls of adjacent metal wiring patterns using a spin-on method and removing a portion of the SiOC layer by dry etching until the first dielectric layer on the plurality of metal wiring patterns is exposed, the SiOC layer having a lower dielectric constant than the first dielectric layer; and

(e) forming a second dielectric layer on the SiOC layer and the exposed first dielectric layer.

2. The method of claim 1 , wherein the first dielectric layer covers a profile of the plurality of metal wiring patterns, and produces a gap encompassed by the first dielectric layer between adjacent metal wiring patterns.

3. The method of claim 1 , wherein the second dielectric layer comprises substantially a same material as the first dielectric layer.

4. The method of claim 1 , wherein the method further includes the step of forming a third planarized dielectric layer after step (e).

5. The method of claim 1 , wherein the intermetal dielectric layer comprises the first and second dielectric layers and the SiOC layer.

6. The method of claim 1 , further comprising etching the first dielectric layer and the intermetal dielectric layer to form via holes exposing a portion of an upper surface of the metal wiring patterns.

7. The method of claim 2 , wherein step (d) comprises the steps of: (d1) depositing the SiOC material on the first dielectric layer; (d2) filling the gap with the SiOC material by rotating the substrate; and (d3) solidifying and/or densifying the SiOC material by heat-treatment, thereby forming the SiOC layer between adjacent metal wiring patterns.

8. The method of claim 5 , further comprising forming a third dielectric layer on the second dielectric layer, and planarizing the third dielectric layer.

9. A method for forming an intermetal dielectric layer, comprising the steps of:

(a) forming a metal layer comprising a plurality of metal wires or lines;

(b) conformally depositing a first dielectric layer on the plurality of metal wires or lines;

(c) forming a SiOC layer on portions of the first dielectric layer above the metal wiring patterns and in a gap between sidewalls of adjacent metal wiring patterns using a spin-on method and removing a portion of the SiOC layer by dry etching until the first dielectric layer on the plurality of metal wiring patterns is exposed, the SiOC layer having a lower dielectric constant than the first dielectric layer; and

(d) forming a second dielectric layer on the SiOC layer and the exposed first dielectric layer.

10. The method of claim 9 , wherein adjacent metal wires or lines have a gap therebetween, and the first dielectric layer has a thickness of less than half of a width of the gap.

11. The method of claim 9 , wherein step (c) comprises depositing the SiOC material on the first dielectric layer while rotating the substrate.

12. The method of claim 9 , wherein the second dielectric layer comprises substantially a same material as the first dielectric layer.

13. The method of claim 9 , wherein the method further includes, after step (d), the step of forming a third dielectric layer on the second dielectric layer, and planarizing the third dielectric layer.

14. The method of claim 9 , wherein the method further includes forming via holes over the plurality of metal wiring patterns, exposing a portion of an upper surface of the metal wiring patterns.

15. The method of claim 11 , further comprising heating the SiOC material to solidify or densify it, thereby forming the SiOC layer between adjacent metal wires or lines.

16. The method of claim 13 , further comprising etching the first, second, and third dielectric layers to form via holes exposing a portion of an upper surface of the metal wiring patterns.