Trench field plate termination for power devices
In accordance with an embodiment of the invention, a semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. A first silicon region of a first conductivity type extends to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. At least one termination trench is formed in the termination. The termination trench extends into the second silicon region, and is laterally spaced from the first silicon region. An insulating layer lines the sidewalls and bottom of the termination trench. A conductive electrode at least partially fills the termination trench.
1. A semiconductor power device comprising:
an active region configured to conduct current when the semiconductor device is biased in a conducting state; and
a termination region along a periphery of the active region, the termination region comprising:
a first silicon region of a first conductivity type extending to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween;
a first termination trench extending into the second silicon region, and being laterally spaced from the first silicon region;
an insulating layer lining the sidewalls and bottom of the first termination trench; and
a conductive electrode at least partially filling the first termination trench.
2. The semiconductor power device of claim 1 wherein the conductive electrode is configured to form a field plate which spreads the electric field in the second silicon region in a substantially uniform fashion when the PN junction is reverse biased.
3. The semiconductor power device of claim 1 wherein the conductive electrode completely fills the first termination trench and extends out of the first termination trench to electrically contact a surface of the second silicon region.
4. The semiconductor power device of claim 3 wherein the conductive electrode and the second silicon region are of opposite conductivity type.
5. The semiconductor power device of claim 3 further comprising a highly doped silicon region of the second conductivity type extending into the second silicon region, and being configured so as to reduce a contact resistance of the contact between the conductive electrode and the second silicon region.
6. The semiconductor power device of claim 1 wherein the conductive electrode is recessed in the first termination trench and is fully insulated from the second silicon region, and an interconnect layer electrically connects the conductive electrode to the first silicon region.
7. The semiconductor power device of claim 6 wherein the first silicon region is electrically unbiased so that it floats during operation.
8. The semiconductor device of claim 6 wherein the semiconductor device is a MOSFET having a drain electrode and a source electrode, the first silicon region being electrically connected to the source terminal.
9. The semiconductor power device of claim 6 further comprising a highly doped silicon region of the first conductivity type extending into the first silicon region, and being configured so as to reduce a contact resistance of the contact between the interconnect layer and the first silicon region.
10. The semiconductor power device of claim 1 wherein the second silicon region comprises an epitaxial layer formed over a substrate.
11. The semiconductor power device of claim 1 wherein the termination trench extends to a depth below the first depth.
12. The semiconductor power device of claim 1 wherein the termination region further comprises:
a second termination trench extending into the second silicon region, and being laterally spaced from the first termination trench;
an insulating layer lining the sidewalls and bottom of the second termination trench; and
a conductive electrode at least partially filling the second termination trench.
13. The semiconductor power device of claim 1 wherein the first silicon region is electrically unbiased so that it floats during operation.
14. The semiconductor device of claim 1 wherein the semiconductor device is a MOSFET having a drain electrode and a source electrode, the conductive electrode being electrically connected to the source terminal.
15. A method of forming a semiconductor power device having an active region configured to conduct current when the semiconductor device is biased in a conducting state and a termination region along a periphery of the active region, the method comprising:
forming a first silicon region of a first conductivity type extending to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween;
forming at least one termination trench in the termination region, the at least one termination trench extending into the second silicon region and being laterally spaced from the first silicon region;
forming an insulating layer lining the sidewalls and bottom of the at least one termination trench; and
forming a conductive electrode at least partially filling the at least one termination trench.
16. The method of claim 15 wherein the step of forming a conductive electrode is carried out so that the conductive electrode completely fills the at least one termination trench and extends out of the at least one termination trench to electrically contact a surface of the second silicon region.
17. The method of claim 15 wherein the conductive electrode and the second silicon region are of opposite conductivity type.
18. The method of claim 15 wherein the conductive electrode is recessed in the termination trench and is fully insulated from the second silicon region, the method further comprising:
forming an interconnect layer electrically connects the conductive electrode to the first silicon region.