Methods of forming interconnection lines in semiconductor devices
View Patent ↗The present disclosure improves characteristics and reliability of a device by preventing seams within a copper layer, wherein seams are created when forming a copper line by a damascene process. Such seams created within a first and a second copper layer are prevented by a process in which the first copper layer and the second copper layer are deposited at constant speeds when the first copper layer is firstly formed only in a via hole by leaving a first copper seed layer only in the via hole, and then the second copper layer is formed in a trench by forming a second copper seed layer in the trench.
1. A method of forming an interconnection line in a semiconductor device, comprising:
forming an insulating layer on a semiconductor substrate;
forming a via hole to partially expose the semiconductor substrate by etching the insulating layer;
forming a first copper seed layer on the via hole and a surface of the insulating layer;
forming a first photoresist layer on the first copper seed layer, the first photoresist layer filling the via hole;
forming a line-shaped trench over the first photoresist layer in the via hole by sequentially etching the first photoresist layer, a portion of the first copper seed layer, and an upper part of the insulating layer;
forming a damascene structure including the via hole and the trench by removing the first photoresist layer in the via hole to expose the first copper seed layer in the via hole;
forming a first copper layer that fills the via hole and has a top portion protruding into a bottom portion of the trench on the exposed first copper seed layer;
removing a remaining portion of the first photoresist layer on the insulating layer;
forming a second copper seed layer on an entire surface of the substrate; and
forming a second copper layer on the insulating layer and in the trench using the second copper seed layer.
2. The method of claim 1 , wherein the forming of the trench comprises:
forming an internal layer on the first photoresist layer;
forming a second photoresist pattern on the internal layer to expose the via hole and the internal layer around the via hole;
etching the internal layer using the second photoresist pattern as a mask;
sequentially etching the first photoresist layer, the first copper seed layer, and an upper part of the insulating layer using the internal layer and the second photoresist pattern as a mask; and
sequentially removing the second photoresist pattern and the internal layer.
3. The method of claim 2 , wherein the internal layer comprises an insulating layer or a polysilicon layer.
4. The method of claim 3 , wherein the insulating layer comprises an oxide or a nitride.
5. The method of claim 2 , wherein the first photoresist layer in the via hole is removed while removing the second photoresist pattern.
6. The method of claim 1 , wherein the first copper layer is deposited at a first substantially constant deposit speed.
7. The method of claim 6 , wherein the second copper layer is deposited at a second substantially constant deposit speed.
8. The method of claim 1 , wherein the insulating layer comprises a low K dielectric material.
9. The method of claim 1 , wherein the insulating layer has a dielectric constant of less than about 3.0.
10. The method of claim 1 , wherein the insulating layer comprises an oxide layer or a nitride layer.
11. The method of claim 1 , wherein forming the first copper seed layer comprises electroplating.
12. The method of claim 1 , wherein forming the second copper layer comprises electroplating.
13. The method of claim 1 , wherein the step of removing the first photoresist layer comprises dry etching the first photoresist layer.
14. The method of claim 3 , wherein the insulating layer comprises a polyimide, an organic polymer, an inorganic polymer, silicon oxide, silicon nitride, a spin-on-glass material or a combination Thereof.
15. The method of claim 1 , further comprising removing the second copper layer by chemical mechanical polishing to expose the insulating layer and form an upper copper line.
16. The method of claim 1 , further comprising forming a lower copper line on the semiconductor substrate prior to forming the insulating layer.
17. The method of claim 16 , wherein the via, hole exposes the lower copper line.
18. The method of claim 1 , wherein the trench is wider than the via hole.
19. The method of claim 1 , further comprising forming a diffusion barrier layer on the semiconductor substrate prior to forming the insulating layer.
20. The method of claim 19 , wherein the diffusion barrier layer comprises silicon nitride.