Semiconductor device
View Patent ↗A semiconductor device includes a substrate including a high-voltage transistor area provided with a high-voltage transistor and a low-voltage transistor area provided with a low-voltage transistor; a LOCOS layer provided as a device isolation layer of the high-voltage transistor area; and a shallow-trench isolation layer provided as a device isolation layer of the low-voltage transistor area. Accordingly, a sufficient breakdown voltage level can be provided in a high-voltage transistor area, on-resistance and leakage current can be enhanced, and the chip area in a low-voltage transistor area can be reduced.
1. A method of fabricating a semiconductor device, comprising:
providing a substrate including a high-voltage transistor area provided with a high-voltage transistor having a breakdown voltage of not less than 30V and a low-voltage transistor area provided with a low-voltage transistor;
providing a LOCOS layer in a high-voltage transistor area; and
providing a shallow-trench isolation layer in a low-voltage transistor area.
2. The method of claim 1 , wherein providing a LOCOS layer comprises:
forming a well in a high-voltage transistor area by ion implantation and annealing; and forming an extended drain region.
3. The method of claim 2 , wherein providing a LOCOS layer further comprises:
depositing a pad oxide layer over a substrate;
depositing a pad nitride layer on the pad oxide layer;
depositing a photoresist on the pad nitride layer;
selectively etching and developing the photoresist to expose a surface of the substrate and to form a photoresist pattern;
etching a trench into the high-voltage transistor area using the photoresist pattern as a mask for the low-voltage transistor area;
thermally oxidizing the substrate to form the LOCOS layer on the exposed surface of the substrate; and
removing the photoresist pattern.
4. The method of claim 1 , wherein providing a shallow-trench isolation layer comprises:
depositing a photoresist on a substrate;
selectively etching and developing the photoresist to expose a surface of the substrate and to form a photoresist pattern;
etching a pad nitride layer and a pad oxide layer in the low-voltage transistor area using the photoresist pattern as a mask for the high-voltage transistor area;
removing the photoresist pattern;
etching the substrate using the etched pad nitride layer and the etched pad oxide layers as a mask, thereby forming an STI trench;
forming an oxide liner in the STI trench by a thermal treatment process;
depositing an insulating material over the substrate including the STI trench, thereby filling the STI trench with the insulating material;
planarizing the insulating material; and
performing a treatment to strip the pad nitride layer in the low-voltage transistor area.