Delay circuit and semiconductor device

1. A delay circuit for delaying an input signal with an edge at a predetermined timing and outputting a delayed signal, comprising:

N-stage circuits (where N is an integer greater than, or equal to, 2) having a first circuit to an N-th circuit connected in cascade, said input signal being input to said first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for sequential transmission;

a common delay circuit for delaying said transmission signal of each stage of said N-stage circuits commonly; and

path control means for controlling a path of an i-th (1≦i≦N) circuit of said N-stage circuits so that during a predetermined period from an edge timing of a signal input to said i-th circuit to an edge timing of said transmission signal delayed by said common delay circuit through said i-th circuit, said common delay circuit is connected to a signal path, and during the other period, said common delay circuit is disconnected from said signal path,

wherein said delayed signal passing through said common delay circuit N times in the path of said N-stage circuits is generated.

2. A delay circuit according to claim 1 , wherein said transmission signal of each stage of said N-stage circuits is delayed by a unit delay time Δt, and each said i-th circuit outputs a delayed signal having an accumulated delay time iΔt.

3. A delay circuit according to claim 1 , wherein each stage of said N-stage circuits includes an input-side circuit which connects an input-side signal path to an input of said common delay circuit and an output-side circuit which connects an output of said common delay circuit to an output-side signal path,

and wherein said path control means includes switching means for switching the connection of both said input-side and output-side circuits of each stage of said N-stage circuits between on and off.

4. A delay circuit according to claim 3 , wherein said switching means comprises a tri-state inverter capable of switching between an inverter operation and a high-impedance state in response to an enable signal, said enable signal is commonly applied to each tri-state inverter of both said input-side and output-side circuits of each stage of said N-stage circuits, and switching is controlled so that said tri-state inverter is in said inverter operation during said predetermined period and said tri-state inverter is in said high-impedance state during the other period.

5. A delay circuit according to claim 1 , wherein in said N-stage circuit, each said transmission signal of odd number stage circuits is logically inverted to each said transmission signal of even number stage circuits.

6. A delay circuit according to claim 1 , wherein said switching means supplies a reset signal for initializing switching operation to said N-stage circuits and said common delay circuit,

and wherein after an edge timing of said input signal and all edge timings of N delayed signals extracted from the stages of said N-stage circuits are elapsed, said reset signal is controlled to be supplied for initializing.

7. A delay circuit according to claim 6 , wherein said reset signal is generated based on said input signal of the first stage circuit.

8. A semiconductor device comprising a circuit including the delay circuit of any of claims 1 to 7 .

9. A semiconductor device according to claim 8 , wherein N delayed signals extracted from the stages of said N-stage circuits are used as control signals for use in refresh operation of a semiconductor memory.