IP Library Granted Patent US 7,413,977
Granted Patent B2
US 7,413,977 · App. 11/318,530 · Granted Aug 19, 2008

Method of manufacturing semiconductor device suitable for forming wiring using damascene method

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Quick Facts
Patent No.
US 7,413,977
App. No.
11/318,530
Granted
Aug 19, 2008
Kind
B2
Abstract

A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. Then a first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. Then conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. Then the semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.

Claims (10)

1. A semiconductor device manufacture method comprising steps of:

(a1) forming a concave portion in an interlayer insulating film formed over a semiconductor substrate;

(a2) forming a first film of Mn by CVD, the first film covering an inner surface of the concave portion and an upper surface of the insulating film;

(a3) depositing conductive material essentially consisting of Cu on the first film to embed the conductive material in the concave portion; and

(a4) annealing the semiconductor substrate.

2. The semiconductor device manufacture method according to claim 1 , wherein the step (a3) comprises steps of:

forming a second film of Cu by CVD or sputtering, the second film covering a surface of the first film; and

electroplating conductive material essentially consisting of Cu, by using the second film as an electrode.

3. The semiconductor device manufacture method according to claim 1 , wherein in the step (a3), the conductive material is embedded in the concave portion by depositing the conductive material essentially consisting of Cu using CVD.

4. The semiconductor device manufacture method according to claim 1 , wherein in the step (a2), bismethylcyclopentadienyl manganese or bisisopropylcyclopentadienyl manganese is used as Mn source.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2005
From: SHIMIZU, NORIYOSHI; OHTSUKA, NOBUYUKI; KITADA, HIDEKI; NAKAO, YOSHIYUKI
To: FUJITSU LIMITED
Reel/Frame 017424/0782 →