Semiconductor storage device
View Patent ↗An SRAM cell 1 includes inverters 10, 20 , N-type FETs 32, 34, 36, 38 , word lines 42, 44 , bit lines 46, 48 , and voltage applying circuits 50, 60 . The voltage applying circuits 50, 60 apply a voltage V dd to the word lines 42, 44 at the time of a read operation of the SRAM cell 1 . The voltage applying circuits 50, 60 apply a voltage (V dd +α) to the word lines 42, 44 at the time of a write operation of the SRAM cell 1 . Here, α>0. Namely, the SRAM cell 1 is configured in such a manner that a voltage applied to word lines 42, 44 at the time of the write operation is higher than at the time of the read operation.
1. A semiconductor storage device comprising an SRAM cell having a first inverter, a second inverter with an input terminal and output terminal connected to an output terminal and input terminal of said first inverter respectively, a first pass transistor provided in a path between said output terminal of said first inverter and a first bit line, a second pass transistor provided in a path between said output terminal of said second inverter and a second bit line, and a word line connected to gates of said first and second pass transistors;
wherein said SRAM cell comprising:
a third pass transistor provided in a path between said first pass transistor and said first bit line;
a fourth pass transistor provided in a path between said second pass transistor and said second bit line; and
a voltage applying unit applying a first voltage to said word line at the time of a read operation of said SRAM cell, and applying a second voltage larger than said first voltage to said word line at the time of a write operation of said SRAM cell.
2. The semiconductor storage device according to claim 1 , wherein said voltage applying unit comprises a decoder outputting said first voltage, and a step-up circuit outputting said second voltage at the time of said write operation by stepping up said first voltage outputted by said decoder.
3. The semiconductor storage device according to claim 1 ,
said SRAM cell further comprising:
a fifth pass transistor, of an opposite conductive type to said first pass transistor, connected in parallel with said first pass transistor; and
a sixth pass transistor, of an opposite conductive type to said second pass transistor, connected in parallel with said second pass transistor.
4. The semiconductor storage device according to claim 1 , said SRAM cell further comprising:
a fifth pass transistor, of an opposite conductive type to said third pass transistor, connected in parallel with said third pass transistor; and
a sixth pass transistor, of an opposite conductive type to said fourth pass transistor, connected in parallel with said fourth pass transistor.