Method of fabricating fin field-effect transistors
View Patent ↗A method of fabricating a fin field-effect transistor that may enable a reduction in the number of process steps, by forming the fin structure by etching away a predetermined thickness of an element isolation layer. The method includes steps of sequentially forming a first insulating layer and a second insulating layer on a region of a substrate excluding an inactive region thereof; forming a trench of the inactive region of the substrate by using the first and second insulating layers as a mask; forming an element isolation layer in the trench; and removing the first insulating layer and the second insulating layer and, at the same time, removing a predetermined thickness of the element isolation layer.
1. A method of fabricating a fin field-effect transistor, comprising:
sequentially forming a first insulating layer and a second insulating layer on an active region of a substrate;
forming a trench in an inactive region of the substrate by using the first and second insulating layers as a mask;
forming an element isolation layer in the trench; and
removing the second insulating layer; and
simultaneously removing the first insulating layer and a predetermined thickness of the element isolation layer,
wherein the active region of the substrate protrudes upwardly higher than the element isolation layer.
2. The method of claim 1 , further comprising forming a well region in the active region of the substrate that protrudes upwardly higher than the element isolation layer.
3. The method according to claim 1 , wherein forming the element isolation layer comprises:
forming a third insulating layer on the entire surface of the substrate where the trench is formed; and
performing chemical-mechanical polishing to the third insulating layer until the second insulating layer is exposed.
4. The method according to claim 1 , further comprising:
implanting ions into the active region to form a well region;
forming a gate electrode in the active region; and
implanting ions on both sides of the gate electrode to form a source/drain region.
5. The method according to claim 4 , further comprising:
forming a spacer on the sidewall of the gate electrode; and
forming a heavily doped junction region of the source/drain region by using the spacer as a mask.
6. The method according to claim 5 , wherein the heavily doped junction region of the source/drain region extends past the top surface of the element isolation layer.
7. The method according to claim 6 , wherein the heavily doped junction region of the source/drain region extend past the top surface of the element isolation layer by at least 500 angstroms.
8. The method according to claim 6 , further comprising:
forming a silicide over the gate electrode; and
forming a silicide over the source/drain region.
9. The method according to claim 8 , wherein the silicide over the source/drain region extends from the spacer to the element isolation layer.
10. The method of claim 1 , wherein the first insulating layer is a pad oxide layer.
11. The method of claim 1 , wherein the second insulating layer is a pad nitride layer.
12. The method of claim 1 , wherein a rinsing process using a sequence of solutions is employed after the formation of the element isolation layer.
13. The method of claim 12 , wherein the sequence of solutions comprises H 2 SO 4 , NH4, OH, and HF.
14. The method of claim 12 , wherein the sequence of solutions comprises H 2 SO 4 , H 2 O 2 , NH 4 OH, HF, and BOE.