IP Library Granted Patent US 7,556,998
Granted Patent B2
US 7,556,998 · App. 11/319,489 · Granted Jul 7, 2009

Method of manufacturing semiconductor devices

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Quick Facts
Patent No.
US 7,556,998
App. No.
11/319,489
Granted
Jul 7, 2009
Kind
B2
Abstract

A method of manufacturing a semiconductor device including forming a dummy gate electrode which is divided into first and second areas, selectively implanting N-type ions and P-type ions into the first and second areas of the dummy gate electrode respectively and then implanting impurity ions into a boundary region between the first area and second area of the dummy gate electrode.

Claims (13)

1. A method of manufacturing a semiconductor device, the method comprising:

preparing a semiconductor substrate in which an NMOS area, a PMOS area, an inactive area, and a test area are defined;

forming an element isolating layer in the inactive area of the semiconductor substrate;

forming a gate electrode in the active area of the NMOS area and the active area of the PMOS area; and

forming a dummy gate electrode, which is made of the same material as the gate electrode and which is divided into a plurality of first areas and second areas, in the test area;

selectively implanting N-type ions with a low concentration into a low-concentration junction region of the NMOS area and the plurality of first areas of the dummy gate electrode;

selectively implanting P-type ions with a low concentration into a low-concentration junction region of the PMOS area and the plurality of second areas of the dummy gate electrode;

selectively implanting N-type ions with a high concentration into the low-concentration junction region of the NMOS region and the plurality of first areas of the dummy gate electrode;

selectively implanting P-type ions with a high concentration into the low-concentration junction region of the PMOS region and the plurality of second areas of the dummy gate electrode; and

implanting impurity ions into a boundary region between the plurality of first areas and the plurality of second areas of the dummy gate electrode.

2. The method according to claim 1 , wherein N-type ions with a high concentration are implanted into the boundary region between the plurality of first areas and the plurality of second areas of the dummy gate electrode.

3. The method according to claim 1 , wherein P-type ions with a high concentration are implanted into the boundary region between the plurality of first areas and the plurality of second areas of the dummy gate electrode.

4. The method according to claim 1 , further comprising forming a salicide over the dummy gate.

Assignments (2)
CHANGE OF NAME Recorded Jun 15, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018176/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2005
From: PARK, HYUK; KEUM, DONG YEOL
To: DONGBUANAM SEMICONDUCTOR, INC.
Reel/Frame 017389/0073 →