Method for manufacturing semiconductor device including MIM capacitor
View Patent ↗A semiconductor device including a metal-insulator-metal (MIM) capacitor is manufactured such that a via for connecting upper and lower conductive layers is formed through an insulating interlayer after a silicon nitride layer is deposited as a thick layer on the insulating interlayer. This protects an edge of a MIM structure during an etching process that forms the via. In addition, a fluorine gas can be used in a gas stripping process to remove a polymer residue when stripping the photoresist used to form the via. The MIM capacitor has an insulator layer. The method of manufacturing the device includes forming an insulator layer of the MIM capacitor to a predetermined thickness on the insulating interlayer. The predetermined thickness is equal to the desired thickness plus an augmentation thickness, and the augmentation thickness is determined according to the stripping process for removing the photoresist pattern.
1. A method of manufacturing a semiconductor device including a metal-insulator-metal (MIM) capacitor, comprising:
forming a lower wiring layer;
forming an insulating interlayer on the lower wiring layer;
forming an insulator layer made of nitride on an upper surface of the insulating interlayer to a predetermined thickness;
forming a photoresist pattern for via formation;
forming a via by an etching process performed on the insulating interlayer; and
removing the photoresist pattern using a gas stripping process,
wherein the predetermined thickness is equal to a desired thickness plus an augmentation thickness, the desired thickness is approximately 650 to 750 Å, and the augmentation thickness is 300 Å.
2. The method of claim 1 , wherein the gas stripping process thins the insulator layer by approximately 200 to 400 Å.
3. The method of claim 1 , wherein the predetermined thickness is 1,000 Å.
4. The method of claim 1 , wherein the etching process comprises:
forming the photoresist pattern on the insulator layer made of nitride;
etching the insulator layer made of nitride and the insulating interlayer according to the photoresist pattern; and
removing the photoresist pattern after said etching.
5. The method of claim 4 , wherein forming the photoresist pattern comprises:
depositing photoresist layer on the insulator layer made of nitride; and
subjecting the photoresist layer to exposure and development processing.
6. The method of claim 4 , wherein etching the insulator layer made of nitride and the insulating interlayer forms a contact hole exposing a pad surface area of the lower wiring layer.
7. The method of claim 1 , wherein the gas stripping process is an O2 stripping process.
8. The method of claim 7 , wherein the gas of the gas stripping process is a fluorine group gas.
9. The method of claim 8 , wherein the gas of the gas stripping process is one selected from CF 4 , C 2 F 6 , and SF 6 .
10. The method of claim 7 , wherein the gas stripping process removes a polymer residue from a surface of the insulator layer made of nitride formed in a MIM edge region.
11. The method of claim 1 , wherein the insulator layer made of nitride is formed of silicon nitride.
12. The method of claim 1 , wherein the insulating interlayer is formed of an oxide.
13. The method of claim 1 , wherein the insulating interlayer and the insulator layer are formed to have a high etching selectivity ratio of the insulating interlayer to the insulator layer.
14. The method of claim 1 , further comprising:
patterning a metal layer of copper to form a lower electrode of the MIM capacitor on a surface of a semiconductor substrate;
forming the insulator layer to include silicon on the lower electrode; and
patterning a metal layer of copper to form an upper electrode of the MIM capacitor of a patterned copper layer on the insulator layer.