Method of dual bird's beak LOCOS isolation
View Patent ↗A method of dual bird's beak LOCOS may reduce a design rule for a more cost-effective logic device formation. The method may also form a LOCOS layer having a smooth bird's beak to fabricate a stable high-voltage device. The method includes steps of defining a low-voltage device area for a logic device and a high-voltage device area for a high-voltage device, forming a first pad layer in the low-voltage device area and a second pad layer in the high-voltage device area, the first pad layer being thinner than the second pad layer, and forming LOCOS type device isolation layers having bird's beaks differing in size in each of the low-voltage device area and the high-voltage device area, by oxidizing a portion of the semiconductor substrate exposed by a hard mask.
1. A method of dual bird's beak LOCOS isolation, comprising:
defining in a semiconductor substrate a low-voltage device area for a logic device and a high-voltage device area for a high-voltage device;
forming a pad layer on the semiconductor substrate;
selectively etching the pad layer in the low-voltage device area to reduce a thickness of the pad layer to form a first pad layer in the low-voltage device area and a second pad layer in the high-voltage device area, the first pad layer being thinner than the second pad layer;
forming a hard mask on the first pad layer and the second pad layer; and
forming at least one LOCOS type device isolation layer having bird's beaks differing in size in each of the low-voltage device area and the high-voltage device area, by oxidizing a portion of the semiconductor substrate exposed by the hard mask.
2. The method of claim 1 , wherein forming a hard mask comprises:
depositing a silicon nitride layer on the first pad layer and the second pad layer; and
patterning the deposited silicon nitride layer.
3. The method of claim 1 , wherein the low-voltage device area includes a first device isolation layer having a first bird's beak, wherein the high-voltage device area includes a second device isolation layer having a second bird's beak, and wherein the first bird's beak is smaller than the second bird's beak by a thickness difference between the first pad layer and the second pad layer.
4. A method of dual bird's beak LOCOS isolation, comprising:
defining in a semiconductor substrate a low-voltage device area for a logic device and a high-voltage device area for a high-voltage device;
forming a pad layer on the semiconductor substrate;
depositing a mask layer on the pad layer;
selectively etching the mask layer in the low-voltage device area to reduce a thickness of the mask layer to form, on the pad layer, a first hard mask layer in the low-voltage device area and a second hard mask layer in the high-voltage device area, the first hard mask layer being thicker than the second hard mask layer;
patterning the first hard mask layer and the second hard mask layer to form a first hard mask and a second hard mask, respectively; and
forming at least one LOCOS type device isolation layer having bird's beaks differing in size in each of the low-voltage device area and the high-voltage device area, by respectively oxidizing portions of the semiconductor substrate exposed by the first hard mask and the second hard mask.
5. The method of claim 4 , further comprising:
depositing a silicon nitride layer on the pad layer.
6. The method of claim 4 , wherein the low-voltage device area includes a first device isolation layer having a first bird's beak, wherein the high-voltage device area includes a second device isolation layer having a second bird's beak, and wherein the first bird's beak is smaller than the second bird's beak by a thickness difference between the first hard mask and the second hard mask.
7. A method of dual bird's beak LOCOS isolation, comprising:
defining in a semiconductor substrate a low-voltage device area for a logic device and a high-voltage device area for a high-voltage device;
forming a pad layer on the semiconductor substrate;
selectively etching the pad layer in the low-voltage device area to reduce a thickness of the pad layer to form a first pad layer in the low-voltage device area and a second pad layer in the high-voltage device area, the first pad layer being thinner than the second pad layer;
forming a first hard mask layer on the first pad layer and a second hard mask layer on the second pad layer, the first hard mask layer being thicker than second hard mask layer;
patterning the first hard mask layer and the second hard mask layer to form a first hard mask and a second hard mask, respectively; and
forming at least one LOCOS type device isolation layer having bird's beaks differing in size in each of the low-voltage device area and the high-voltage device area, by respectively oxidizing portions of the semiconductor substrate exposed by the first hard mask and the second hard mask.
8. The method of claim 7 , said first and second hard mask forming comprising:
depositing a hard mask layer on the first and second pad layers; and
selectively etching the hard mask layer covering the second pad layer to reduce a thickness of the etched hard mask layer.
9. The method of claim 8 , further comprising:
depositing a silicon nitride layer on the pad layer.
10. The method of claim 7 , wherein the low-voltage device area includes a first device isolation layer having a first bird's beak, wherein the high-voltage device area includes a second device isolation layer having a second bird's beak, and wherein the first bird's beak is smaller than the second bird's beak by a thickness difference between the first pad layer and the second pad layer and a thickness difference between the first hard mask and the second hard mask.