Flash memory device and a method of manufacturing the same
View Patent ↗The present invention provides a flash memory device and a method of forming the same. The method includes: forming an isolation layer and a plurality of gate lines on a semiconductor substrate; forming a source/drain region by ion-implanting impurities into the semiconductor substrate using the gate lines as a mask; forming a side oxide layer on sidewalls and surfaces of the gate lines; forming a side nitride layer on the side oxide layer; forming an insulation layer on the semiconductor substrate and the side nitride layer; forming a photosensitive layer pattern on the insulation layer; exposing the source region between the gate lines by etching the insulation layer using the photosensitive layer pattern as a mask; forming a polysilicon layer on the exposed source region and the insulation layer; and forming a source line by etching the polysilicon layer.
1. A method of manufacturing a flash memory device, comprising:
forming isolation layers and a plurality of gate lines on a semiconductor substrate;
forming source and drain regions by ion-implanting impurities into the semiconductor substrate using the gate lines as a mask;
forming a side oxide layer on sidewalls and surfaces of the gate lines;
forming a side nitride layer on the side oxide layer;
forming an insulation layer on the semiconductor substrate and the side nitride layer;
forming a photosensitive layer pattern on the insulation layer;
exposing the source regions between the gate lines by etching the insulation layer using the photosensitive layer pattern as a mask;
forming a polysilicon layer on the exposed source regions and the insulation layer; and forming a source line by etching the polysilicon layer so that the source line is laterally connected to the source regions;
wherein the insulation layer is removed after forming the source line; and
wherein the etching of the polysilicon layer is performed by a chemical mechanical polishing process or plasma etching process.
2. The method of claim 1 , wherein the forming of a plurality of gate lines comprises:
forming a first oxide layer on the semiconductor substrate; forming a first polysilicon layer on the first oxide layer;
removing the first oxide layer by using the first polysilicon layer as a mask;
forming a second oxide layer on the first polysilicon layer; and
forming a second polysilicon layer on the second oxide layer and the isolation layer.
3. The method of claim 1 , wherein the source region is formed between the isolation layers that are located between the gate lines.
4. The method of claim 1 , wherein the isolation layer is formed in parallel with a bit line direction.
5. The method of claim 1 , wherein the source line is formed in a straight line shape between the gate lines.
6. The method of claim 5 , wherein the gate line is formed in parallel with the word line direction.