Methods of fabricating MIM capacitors
View Patent ↗Methods of fabricating MIM capacitors are provided. One example method includes forming an insulating layer including a void on a semiconductor substrate, forming a first hole connected to the void by patterning the insulating layer, forming a lower electrode by forming a tungsten layer filling in the first hole such that the tungsten flows into the void, forming a dielectric layer, forming a second hole penetrating the dielectric layer and protruding toward the insulating layer, forming a connecting contact connected to the lower electrode by filling in the second hole, and forming an upper electrode on the dielectric layer.
1. A method of fabricating a metal-insulator-metal capacitor, comprising:
forming an insulating layer including a void on a semiconductor substrate;
forming a first hole connected to the void by patterning the insulating layer;
forming a lower electrode by forming a conductive layer filling in the first hole such that the conductive layer flows into the void;
forming a dielectric layer covering the conductive layer;
forming a second hole penetrating the dielectric layer and protruding toward the insulating layer;
forming a connecting contact connected to the lower electrode by filling in the second hole; and
forming an upper electrode on the dielectric layer.
2. The method of claim 1 , further comprising forming a pattern for creating a height difference for inducing the void in the insulating layer.
3. The method of claim 2 , wherein the pattern for creating the height difference is formed together with a gate pattern of a transistor on the semiconductor substrate.
4. The method of claim 3 , wherein the pattern for creating the height difference includes a polysilicon layer for the gate of the transistor on the semiconductor substrate.
5. The method of claim 1 , wherein the insulating layer includes a plasma enhanced oxide layer so as to create the void in the insulating layer.
6. The method of claim 5 , wherein the insulating layer includes a TEOS layer as a lower layer of the plasma enhanced oxide layer so as to create the void in the insulating layer.
7. The method of claim 1 , wherein the forming of the lower electrode comprises:
forming a tungsten layer filling in the first hole;
annealing the tungsten layer such that the tungsten may intrude into the void; and
removing a portion of the tungsten layer protruding above the insulating layer.
8. The method of claim 1 , wherein the forming of the second hole and the forming of the connecting contact are performed together while forming other connecting contacts for terminals of the transistor on the semiconductor substrate.
9. The method of claim 1 , wherein the forming of the upper electrode is performed while forming a wire for the operation of the transistor on the semiconductor substrate.