IP Library Granted Patent US 7,645,672
Granted Patent B2
US 7,645,672 · App. 11/319,789 · Granted Jan 12, 2010

Mask ROM, method for fabricating the same, and method for coding the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,645,672
App. No.
11/319,789
Granted
Jan 12, 2010
Kind
B2
Abstract

A mask ROM, a method for fabricating the same and a method for coding the same are disclosed. The method for forming the mask ROM maximizes packing density and integration of a device. The mask ROM includes a semiconductor substrate having a device isolation region and an active region, BN junction regions formed in predetermined portions of the active region, an insulating film, first electrode layers formed on predetermined portions of the insulating film, spacers formed at sides of the first electrode layers, and second electrode layers between the spacers.

Claims (13)

1. A method for fabricating a mask ROM comprising:

depositing an insulating film on a semiconductor substrate having a device isolation region and an active region;

forming BN junction regions by implanting impurity ions to predetermined portions of the substrate, wherein forming the BN junction regions comprises:

depositing a nitride film on the insulating film;

forming nitride film patterns by selectively removing the nitride film;

forming first sidewall spacers at sides of the nitride film patterns;

implanting impurity ions into the semiconductor substrate using the nitride film patterns and the first sidewall spacers as masks to form the BN junction regions; and

removing the nitride film patterns and the spacers;

forming first electrode layers by depositing polysilicon on the insulating film and selectively removing the polysilicon;

forming second sidewall spacers at sides of the first electrode layers; and

forming second electrode layers between the second sidewall spacers.

2. The method of claim 1 , wherein the spacers are formed by an etch-back process after the insulating film is deposited on an entire surface of the semiconductor substrate including the first electrode layers.

3. The method of claim 1 , wherein the second electrode layers have a height equal to that of the first electrode layers.

Assignments (3)
CHANGE OF NAME Recorded Jun 15, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018176/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2006
From: KIM, HEUNG JIN
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 017863/0279 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2006
From: KIM, HEUNG JIN
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 018092/0451 →