Semiconductor device having high-voltage transistor and PIP capacitor and method for fabricating the same
View Patent ↗A semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a method for fabricating the same are provided. A current flow path of the high-voltage transistor is widened to reduce on-resistance of the device. Thus, electric characteristics of the device are enhanced. The semiconductor device includes a substrate having a high-voltage transistor area and a PIP capacitor area, an extended drain region disposed in the high-voltage transistor area and separated from a source region, an impurity region formed in an upper portion of the extended drain region, and a drain region formed on a surface of the substrate and disposed within the impurity region.
1. A method of fabricating a semiconductor device, comprising:
defining a high-voltage transistor area and a polysilicon-insulator-polysilicon (PIP) capacitor area on a substrate;
forming an extended drain region in the high-voltage transistor area;
forming a pad insulating layer on the substrate including the extended drain region;
stacking a polysilicon layer and a mask layer on the pad insulating layer;
patterning the mask layer to expose a PIP capacitor portion of the polysilicon layer;
patterning the mask layer and the polysilicon layer to expose a drain region portion of the pad insulating layer in the high-voltage transistor area; and
implanting impurity ions into the exposed portions of the pad insulating layer and the polysilicon layer to form an impurity region within the extended drain region and a first electrode layer on an ion-implanted portion of the polysilicon layer.
2. The method of claim 1 , further comprising:
removing the mask layer;
forming a gate stack in the high-voltage transistor area;
forming a gate spacer layer on a lateral side of the gate stack;
forming a source region, defined by the gate spacer layer and a drain region, within the impurity region by ion implantation; and
sequentially stacking a dielectric layer and a second electrode layer on a first electrode layer in the PIP capacitor area.
3. The method of claim 1 , wherein the mask layer is formed of oxide.
4. The method of claim 1 , wherein implanting impurity ions is performed by a POCl 3 ion implantation step.