Self-aligned bipolar semiconductor device and fabrication method thereof
View Patent ↗A self-aligned bipolar semiconductor device and a fabrication method thereof are provided. After a silicon layer and a collector contact are formed on a buried collector layer, an oxide dummy pattern is formed on the silicon layer to define both an extrinsic base and an intrinsic base. A polycide layer used as the extrinsic base is formed thereon and selectively removed to expose the dummy pattern. After the exposed dummy pattern is removed, an epitaxial layer used as the intrinsic base is grown on both the silicon layer and the polycide layer, and selectively removed from the top of the polycide layer. An oxide layer and a nitride layer are deposited in sequence thereon, and the nitride layer is blanket-etched to form spacers defining an emitter. After a photoresist pattern is formed to mostly cover the oxide layer and partly expose the oxide layer between the spacers over the intrinsic base, the oxide layer is etched by using the photoresist pattern and the spacers as an etch mask.
1. A method of fabricating a semiconductor device, the method comprising:
forming a silicon layer and a collector contact on a buried collector layer;
forming an oxide dummy pattern on the silicon layer, the oxide dummy pattern defining an extrinsic base and an intrinsic base;
forming a polycide layer on the resultant structure having the dummy pattern, the polycide layer being used as the extrinsic base;
selectively removing the polycide layer such that the dummy pattern is exposed;
completely removing the exposed dummy pattern such that the silicon layer is exposed;
growing an epitaxial layer on both the exposed silicon layer and the polycide layer, the epitaxial layer being used as the intrinsic base;
removing the epitaxial layer from a top of the polycide layer;
conformally depositing an oxide layer and a nitride layer in sequence on both the extrinsic base and the intrinsic base;
blanket-etching the nitride layer to form spacers defining an emitter;
forming a photoresist pattern to mostly cover the oxide layer and partly expose the oxide layer between the spacers over the intrinsic base;
etching the oxide layer by using the photoresist pattern and the spacers as an etch mask; and
forming the emitter connected to the intrinsic base.
2. The method of claim 1 , wherein the epitaxial layer is formed of silicon.
3. The method of claim 1 , wherein the epitaxial layer is formed of silicon germanium.
4. The method of claim 1 , wherein the selectively removing of the polycide layer is performed by CMP process.
5. A semiconductor device fabricated by the method set forth in claim 1 .