Method of manufacturing an isolation layer of a flash memory
View Patent ↗A method including forming a first mask material layer on a semiconductor substrate in order to mask a cell region and to not mask a peripheral circuit region. The method further includes forming a second mask material layer on an entire surface of the substrate in the cell region and peripheral circuit region, simultaneously forming a trench having a first depth in the cell region and a trench having a second depth in the peripheral circuit region, where the second depth is greater than the first depth. The method also includes filling an insulation layer into an entire surface of the substrate including trenches, planarizing the insulation material layer and the second mask material layer to a degree that the first mask material layer is exposed, and respectively forming an STI isolation layer in both the cell region and the peripheral circuit region by removing the first and second mask material layer.
1. A method of manufacturing isolation layers having different depths in a flash memory including a cell region and a peripheral circuit region, the method comprising:
forming a first mask material layer on a semiconductor substrate in order to mask only the cell region;
forming a second mask material layer on an entire surface of the substrate at the cell region whereon the first mask material layer is formed and the peripheral circuit region whereon the first mask material layer is not formed;
simultaneously forming a trench having a first depth in the cell region and a trench having a second depth in the peripheral circuit region by etching the second mask material layer and the substrate in the cell region and the peripheral circuit region, the second depth being greater than the first depth;
filling an insulation layer into the entire surface of the substrate including trenches;
planarizing the insulation material layer and the second mask material layer to a degree that the first mask material layer is exposed; and
respectively forming a shallow trench isolation (STI) layer in both the cell region and the peripheral circuit region by removing the first and second mask material layers,
wherein the second mask material layer is formed to have a height difference between the cell region and the peripheral circuit region.
2. The method of claim 1 , wherein a thin pad insulation layer is formed on the semiconductor substrate in the cell region before forming the first mask material layer.
3. The method of claim 2 , wherein the thin pad insulation layer is a silicon oxide layer.
4. The method of claim 1 , wherein the first mask material layer is a tetraethylorthosilicate (TEOS) layer.
5. The method of claim 1 , wherein the second mask material layer is composed of at least one insulation layer.
6. The method of claim 1 , wherein the second mask material layer is composed of a tetraethylorthosilicate (TEOS) layer and a silicon nitride layer.
7. The method of claim 5 , wherein the second mask material layer is composed of a tetraethylorthosilicate (TEOS) layer and a silicon nitride layer.
8. The method of claim 1 , wherein the first depth has a range from 1000 Å to 2000 Å, and the second depth has a range from 3000 Å to 4000 Å.
9. The method of claim 1 , wherein the planarization process is performed by a chemical mechanical polishing process.
10. A method of manufacturing isolation layers having different depths in a flash memory including a cell region and a peripheral circuit region, the method comprising:
forming a first mask material layer on a semiconductor substrate in order to mask the cell region and to not mask the peripheral circuit region;
forming a second mask material layer on a surface of the substrate at the cell region whereon the first mask material layer is formed and the peripheral circuit region whereon the first mask material layer is not formed;
forming a trench having a first depth in the cell region and a trench having a second depth in the peripheral circuit region by etching the second mask material layer and the substrate in the cell region and the peripheral circuit region, the second depth being greater than the first depth;
filling an insulation layer into the surface of the substrate including trenches;
planarizing the insulation material layer and the second mask material layer to a degree that the first mask material layer is exposed; and
respectively forming a shallow trench isolation (STI) layer in both the cell region and the peripheral circuit region by removing the first and second mask material layers,
wherein the second mask material layer is formed to have a height difference between the cell region and the peripheral circuit region.
11. The method of claim 10 , wherein a thin pad insulation layer is formed on the semiconductor substrate in the cell region before forming the first mask material layer.
12. The method of claim 11 , wherein the thin pad insulation layer is a silicon oxide layer.
13. The method of claim 10 , wherein the first mask material layer is a tetraethylorthosilicate (TEOS) layer.
14. The method of claim 10 , wherein the second mask material layer is composed of at least one insulation layer.
15. The method of claim 10 , wherein the second mask material layer is composed of a tetraethylorthosilicate (TEOS) layer and a silicon nitride layer.
16. The method of claim 15 , wherein the second mask material layer is composed of a tetraethylorthosilicate (TEOS) layer and a silicon nitride layer.
17. The method of claim 10 , wherein the first depth has a range from 1000 Å to 2000 Å, and the second depth has a range from 3000 Å to 4000 Å.
18. The method of claim 10 , wherein the planarization process is performed by a chemical mechanical polishing process.