Method for fabricating a metal-insulator-metal capacitor
View Patent ↗A method fabricating multiple wiring metals in a semiconductor device. The method includes forming a lower wiring metal on a semiconductor substrate, forming an interlayer dielectric on the lower wiring metal, and selectively removing the interlayer dielectric to form a contact dielectric film, a body dielectric film and an opening between the contact and body dielectric films. The method also includes filling the opening with low-k material, forming a capping dielectric on the contact and body dielectric films and the low-k material, forming a contact hole passing through the capping dielectric and the contact dielectric film to be connected to the lower wiring metal, and forming an upper wiring metal electrically interconnected to the lower wiring metal through the contact hole.
1. A method for fabricating multiple wiring metals in a semiconductor device, comprising the steps of:
forming a lower wiring metal on a semiconductor substrate;
forming an interlayer dielectric on the lower wiring metal;
selectively removing the interlayer dielectric to form a contact dielectric film, a body dielectric film and an opening between the contact and body dielectric films;
filling the opening with low-k material;
forming a capping dielectric on the contact and body dielectric films and the low-k material;
forming a contact hole passing through the capping dielectric and the contact dielectric film to be connected to the lower wiring metal; and
forming an upper wiring metal electrically interconnected to the lower wiring metal through the contact hole.
2. The method of claim 1 , wherein the opening exposes the lower wiring metal.
3. The method of claim 1 , wherein a part of the interlayer dielectric remains at a bottom of the opening.
4. The method of claim 1 , wherein the low-k dielectric is at least one of carbonate silicate glass (CSG), alpha-fluorinated amorphous carbon (α-FC), and hydrogen silsesquioxane (HSQ).