IP Library Granted Patent US 7,262,097
Granted Patent B2
US 7,262,097 · App. 11/320,592 · Granted Aug 28, 2007

Method for forming floating gate in flash memory device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,262,097
App. No.
11/320,592
Granted
Aug 28, 2007
Kind
B2
Abstract

A method for fabricating a nonvolatile memory device including successively forming a first oxide layer, an electrically conductive layer, a second oxide layer, a nitride layer and a third oxide layer on a semiconductor substrate. The method also includes patterning the third oxide layer, forming spacers at sidewalls of the third oxide layer, forming a trench in the substrate by selectively etching the substrate with the third oxide layer as a mask, filling the trench with fourth oxide layer, and removing the third oxide layer, the nitride layer and the second oxide layer. Before filling the trench with the fourth oxide layer, a liner oxide layer is formed on inner walls of the trench. The fourth oxide layer is high density plasma (HDP) oxide and tetrafluoroethane (Si(OC 2 H 5 ) 4 ). During the filling the trench, lower corners of the conductive layer are made have rounded structure or bird's beak structure.

Claims (11)

1. A method for fabricating a nonvolatile memory device, said method comprising the steps of:

successively forming a first oxide layer, an electrically conductive layer, a second oxide layer, a nitride layer and a third oxide layer on a semiconductor substrate;

patterning the third oxide layer;

forming spacers at sidewalls of third oxide layer;

forming a trench in the substrate by selectively etching the substrate with the third oxide layer as mask;

forming a liner oxide on inner walls of the trench;

filling the trench with a fourth oxide layer using a semi-recessed LOCOS process, while making lower corners of the conductive layer to have rounded structure, the fourth oxide layer functioning as an isolation layer; and

removing the third oxide layer, the nitride layer and the second oxide layer.

2. The method of claim 1 , wherein the step of removing the third oxide layer, the nitride layer and the second oxide layer is performed by chemical mechanical polishing (CMP) process.

3. The method of claim 1 , wherein the step of forming the trench is carried out by reactive ion etching.

4. The method of claim 1 , wherein the fourth oxide layer is made of high density plasma (HDP) oxide or tetrafluoroethane (Si(OC 2 H 5 ) 4 ).

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041374/0411 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →