Method of manufacturing a gate in a flash memory device

1 . A method of manufacturing a gate in a flash memory device, comprising:

forming a stacking structure including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate on a semiconductor substrate;

removing a remaining portion of the tunnel oxide layer exposed by the control gate by wet etching to a degree that the semiconductor substrate is exposed; and

forming an oxide layer covering the exposed portion of the semiconductor substrate and both sidewalls of the floating gate and control gate.

2 . The method of claim 1 , further comprising:

sequentially depositing an oxide layer, a nitride layer, and a TEOS layer on the semiconductor substrate before forming the tunnel oxide layer on the semiconductor substrate;

forming a trench by etching the oxide layer, the nitride layer, the TEOS layer, and a predetermined depth of the semiconductor substrate using a mask defining active regions on the TEOS layer; and

performing a planarization process for a fill insulation layer filling in the trench.

3 . The method of claim 2 , wherein the fill insulation layer is composed of HDP-USG (High Density Plasma-Undoped Silicate Glass).

4 . The method of claim 1 , wherein the dielectric layer is an ONO (Oxide-Nitride-Oxide) layer.

5 . The method of claim 1 , wherein the wet etching is performed by using an etchant including diluted hydrofluoric acid (DHF).

6 . The method of claim 1 , wherein the oxide layer covering both sidewalls of the gates is formed by performing a rapid thermal annealing (RTA) process.

7 . The method of claim 6 , wherein the rapid thermal annealing (RTA) process is performed at a temperature of 1050° C.

8 . The method of claim 6 , wherein the oxide layer covering both sidewalls of the gates is formed to a uniform thickness of about 60 Å.

9 . The method of claim 1 , wherein the control gate is formed as a control gate of a NOR flash memory cell.